AM29F010B-90JC Spansion Inc., AM29F010B-90JC Datasheet - Page 9

• Manufacturer Part Number: AM29F010B-90JC
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of AM29F010B-90JC

• Memory Size: 1Mbit
• Memory Configuration: 128K X 8
• Ic Interface Type: Parallel
• Access Time: 90ns
• Memory Case Style: PLCC
• No. Of Pins: 32
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.5V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memor y
location. The register is composed of latches that store
the commands, along with the address and data infor-
mation needed to execute the command. The contents
Legend:
L = Logic Low = V
Notes:
1. Addresses are A16:A0.
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at V
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory con-
tent occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the
device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I
table represents the active current specification for
reading array data.
October 31, 2006 Am29F010B_00_C7
Read
Write
Standby
Output Disable
Hardware Reset
tection/Unprotection” section.
IH
Operation
.
IL
, H = Logic High = V
CC1
in the DC Characteristics
Table 1. Am29F010B Device Bus Operations
IL
IH
. CE# is the power
, V
ID
V
CC
= 12.0 ± 0.5 V, X = Don’t Care, A
CE#
± 0.5 V
D A T A
X
L
L
L
Am29F010B
S H E E T
OE#
H
H
of the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
X
X
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the
entire chip.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections for more information.
I
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
L
CC2
in the DC Characteristics table represents the ac-
WE#
IL
H
H
L
X
X
IN
, and OE# to V
= Addresses In, D
Addresses
(Note 1)
IH
A
A
X
X
X
IN
IN
.
IN
= Data In, D
OUT
DQ0–DQ7
High-Z
High-Z
High-Z
D
= Data Out
D
OUT
IN
7