CS4207-CNZ Cirrus Logic Inc, CS4207-CNZ Datasheet - Page 103

• Manufacturer Part Number: CS4207-CNZ
• Description: IC Low Pwr,4/6 HD Aud Codec W/HP Amp
• Manufacturer: Cirrus Logic Inc
• Type: Audio Codecr

Specifications of CS4207-CNZ

• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 3
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 110
• Voltage - Supply, Analog: 2.97 V ~ 5.25 V
• Voltage - Supply, Digital: 2.97 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1796

DS880F1
6.11.11 Mic In 1/Line In 2 EAPD/BTL Enable
6.11.12 Line In 1/Mic In 2 Configuration Default
Get Parameter Command Format:
Set Parameter Command Format:
Get Response Format:
The Configuration Default register is used by software as an aid in determining the configuration of jacks
and devices attached to the codec. At the time the codec is first powered on, this register is internally load-
ed with default values indicating the typical system use of this particular pin/jack. After this initial loading,
it is completely codec opaque, and its state, including any software writes into the register, must be pre-
served across reset events such as LINK Reset or Codec Reset (the Function Reset Verb). Its state need
not be preserved across power level changes.
Get Parameter Command Format:
Set Parameter Command Format:
Response Format
Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits [31:28]
Bits [31:28]
Bits [31:28]
Bits [31:28]
CAd = X
CAd = X
CAd = X
CAd = X
31:3
Bits
Bits
2
1
0
Node ID = 0Dh
Node ID = 0Dh
Node ID = 0Ch
Node ID = 0Ch
Bits [27:20]
Bits [27:20]
Read/Write
Bits [27:20]
Bits [27:20]
Read Only
Read Only
Read Only
Type
Type
Verb ID = F0Ch
Verb ID = F1Ch
Verb ID = 70Ch
Verb ID = 71Ch
Verb ID = 71Dh
Verb ID = 71Eh
Verb ID = 71Fh
Bits [19:8]
Bits [19:8]
Bits [19:8]
Bits [19:8]
Default
Default
0b
0b
0b
0
Reserved
L-R Swap : Not valid since the widget is not
capable of left/right swapping.
EAPD : Not supported on this widget.
BTL: controls the input configuration of a Pin
Widget which has indicated support for balanced
I/O (bit 6, Pin Capabilities Parameter). When this
bit is 0, the inputs are configured in single-ended
or pseudo-differential mode; when this bit is 1,
they are configured in balanced (fully differential)
mode.
Note: This bit is OR’ed with the ADC2 Gain bit in
the
ter of the
ID = 11h)
ADC Configuration (CIR = 0002h)
Vendor Processing Widget (Node
.
Parameter ID = xxh[23:16]
Parameter ID = xxh[31:24]
Parameter ID = xxh[15:8]
Parameter ID = xxh[7:0]
Parameter ID = 00h
Parameter ID = 00h
Parameter ID = xxh
Description
Description
Bits [7:0]
Bits [7:0]
Bits [7:0]
Bits [7:0]
CS4207
Regis-
103