CY7C1361C-100AXCT Cypress Semiconductor Corp, CY7C1361C-100AXCT Datasheet - Page 17

• Manufacturer Part Number: CY7C1361C-100AXCT
• Description: CY7C1361C-100AXCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361C-100AXCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3 V TAP AC Test Conditions
Input pulse levels................................................V
Input rise and fall times....................................................1 ns
Input timing reference levels.......................................... 1.5 V
Output reference levels ................................................. 1.5 V
Test load termination supply voltage ............................. 1.5 V
3.3 V TAP AC Output Load Equivalent
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < T
Identification Register Definitions
Document Number: 38-05541 Rev. *J
V
V
V
V
V
V
I
Revision number (31:29)
Device depth (28:24)
Device width (23:18) 119-BGA
Device width (23:18) 165-FPBGA
Cypress device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID register presence indicator (0)
Notes
X
Parameter
14. All voltages referenced to V
15. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device.
OH1
OH2
OL1
OL2
IH
IL
TDO
A
Instruction Field
< +70 °C; V
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input load current
[15]
Z = 50Ω
Description
DD
O
SS
= 3.3 V ± 0.165 V unless otherwise noted)
(GND).
1.5V
00000110100
CY7C1361C
(256 K × 36)
I
I
I
I
I
I
GND < V
101001
OH
OH
OH
OL
OL
OL
000001
100110
01011
000
20pF
50Ω
= 8.0 mA
= 8.0 mA
= 100 µA
1
= –4.0 mA
= –1.0 mA
= –100 µA
SS
Description
to 3.3 V
IN
< V
DDQ
00000110100
CY7C1363C
(512 K × 18)
101001
000001
010110
01011
000
1
[14]
2.5 V TAP AC Test Conditions
Input pulse levels................................................ V
Input rise and fall time .....................................................1 ns
Input timing reference levels........................................ 1.25 V
Output reference levels ............................................... 1.25 V
Test load termination supply voltage ........................... 1.25 V
2.5 V TAP AC Output Load Equivalent
V
V
V
V
V
V
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
Describes the version number.
Reserved for Internal Use
Defines memory type and architecture
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
TDO
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
= 3.3 V
= 2.5 V
Conditions
CY7C1361C/CY7C1363C
Z = 50Ω
O
Description
–0.5
–0.3
Min
2.4
2.0
2.9
2.1
2.0
1.7
–5
–
–
–
–
1.25V
V
V
DD
DD
Max
0.4
0.4
0.2
0.2
0.7
0.7
–
–
–
–
5
20pF
50Ω
+ 0.3
+ 0.3
Page 17 of 34
SS
to 2.5 V
Unit
µA
V
V
V
V
V
V
V
V
V
V
V
V
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