CY7C68013A-56LTXI Cypress Semiconductor Corp, CY7C68013A-56LTXI Datasheet - Page 10

• Manufacturer Part Number: CY7C68013A-56LTXI
• Description: CY7C68013A-56LTXI
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-56LTXI

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: I2C/USART/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Compliant

3.12 Endpoint RAM
3.12.1 Size
■
■
3.12.2 Organization
■
■
■
■
■
■
Document #: 38-08032 Rev. *M
3× 64 bytes
8 × 512 bytes
EP0
Bidirectional endpoint zero, 64 byte buffer
EP1IN, EP1OUT
64 byte buffers, bulk or interrupt
EP2, 4, 6, 8
Eight 512 byte buffers, bulk, interrupt, or isochronous. EP4 and
EP8 can be double buffered; EP2 and 6 can be either double,
triple, or quad buffered. For high speed endpoint configuration
options, see
Figure
EP0 IN&OUT
(Endpoints 0 and 1)
(Endpoints 2, 4, 6, 8)
EP1 OUT
5.
EP1 IN
EP8
EP2
EP4
EP6
512
512
512
512
512
512
512
512
1
64
64
64
EP4
EP6
EP2
512
512
512
512
512
512
512
512
64
64
64
2
EP2
EP4
EP6
1024
1024
512
512
512
512
64
64
64
3
Figure 5. Endpoint Configuration
EP2
EP8
EP6
512
512
512
512
512
512
512
512
64
64
64
4
EP2
EP6
512
512
512
512
512
512
512
512
64
64
64
5
EP2
EP6
1024
1024
3.12.3 Setup Data Buffer
A separate 8 byte buffer at 0xE6B8-0xE6BF holds the setup data
from a CONTROL transfer.
3.12.4 Endpoint Configurations (High Speed Mode)
Endpoints 0 and 1 are the same for every configuration. Endpoint
0 is the only CONTROL endpoint, and endpoint 1 can be either
BULK or INTERRUPT.
The endpoint buffers can be configured in any 1 of the 12 config-
urations shown in the vertical columns. When operating in the full
speed BULK mode only the first 64 bytes of each buffer are used.
For example, in high speed, the max packet size is 512 bytes but
in full speed it is 64 bytes. Even though a buffer is configured to
a 512 byte buffer, in full speed only the first 64 bytes are used.
The unused endpoint buffer space is not available for other
operations. An example endpoint configuration is the EP2–1024
double buffered; EP6–512 quad buffered (column 8).
512
512
512
512
64
64
64
6
EP2
EP6
EP8
1024
1024
512
512
512
64
64
64
512
7
EP2
1024
1024
EP6
512
512
512
64
64
64
512
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
8
EP2
EP6
1024
1024
1024
1024
64
64
64
9
EP2
EP6
EP8
512
512
512
512
512
512
512
512
64
64
64
10
EP2 EP2
EP8
1024
1024
1024
1024
64
64
64
512
512
11
Page 10 of 62
1024
1024
1024
1024
12
64
64
64
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