CY7C68013A-56LTXI Cypress Semiconductor Corp, CY7C68013A-56LTXI Datasheet - Page 47

• Manufacturer Part Number: CY7C68013A-56LTXI
• Description: CY7C68013A-56LTXI
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-56LTXI

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: I2C/USART/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Compliant

There is no specific timing requirement that should be met for
asserting PKTEND pin to asserting SLWR. PKTEND can be
asserted with the last data value clocked into the FIFOs or there-
after. The setup time t
Although there are no specific timing requirements for the
PKTEND assertion, there is a specific corner case condition that
needs attention while using the PKTEND to commit a one byte
or word packet. There is an additional timing requirement that
needs to be met when the FIFO is configured to operate in auto
mode and it is required to send two packets back to back: a full
packet (full defined as the number of bytes in the FIFO meeting
the level set in AUTOINLEN register) committed automatically
followed by a short one byte or word packet committed manually
using the PKTEND pin. In this scenario, the user must ensure to
assert PKTEND at least one clock cycle after the rising edge that
10.12 Slave FIFO Asynchronous Packet End Strobe
Table 28. Slave FIFO Asynchronous Packet End Strobe Parameters
Document #: 38-08032 Rev. *M
t
t
t
PEpwl
PWpwh
XFLG
PKTEND
FIFOADR
DATA
IFCLK
SLWR
Parameter
PKTEND Pulse Width LOW
PKTEND Pulse Width HIGH
PKTEND to FLAGS Output Propagation Delay
SPE
Figure 23. Slave FIFO Synchronous Write Sequence and Timing Diagram
Figure 24. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
and the hold time t
t
SFA
t
IFCLK
>= t
t
SFD
PKTEND
SWR
X-4
FLAGS
t
FDH
Description
PEH
t
SFD
must be met.
X-3
t
FDH
t
SFD
X-2
t
PEpwl
t
XFLG
t
FDH
caused the last byte or word to be clocked into the previous auto
committed packet.
the AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Figure 23
The first packet gets committed automatically when the number
of bytes in the FIFO reaches X (value set in AUTOINLEN
register) and the second one byte/word short packet being
committed manually using PKTEND.
Note that there is at least one IFCLK cycle timing between the
assertion of PKTEND and clocking of the last byte of the previous
packet (causing the packet to be committed automatically).
Failing to adhere to this timing results in the FX2 failing to send
the one byte or word short packet.
[23]
t
SFD
X-1
t
shows a scenario where two packets are committed.
PEpwh
t
FDH
Min
50
50
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Figure 23
t
SFD
X
t
FDH
At least one IFCLK cycle
shows this scenario. X is the value
Max
115
t
SFD
1
[20]
[20]
>= t
t
FDH
WRH
Page 47 of 62
t
t
FAH
SPE
Unit
ns
ns
ns
t
PEH
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