CY8C3866LTI-023 Cypress Semiconductor Corp, CY8C3866LTI-023 Datasheet - Page 47

• Manufacturer Part Number: CY8C3866LTI-023
• Description: CY8C3866LTI-023
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C38xxr

Specifications of CY8C3866LTI-023

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 67MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x20b, D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 7-13. Digital System Interconnect
Interrupt and DMA routing is very flexible in the CY8C38
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design.
(Interrupt/DMA Multiplexer).
Figure 7-14. Interrupt and DMA Processing in the IDMUX
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
Document Number: 001-11729 Rev. *R
Fixed Function DRQs
Counters
Timer
Global
Clocks
Fixed Function IRQs
Figure 7-14
IO Port
Pins
CAN
UDB Array
EMIF
I2C
shows the structure of the IDMUX
Interrupt and DMA Processing in IDMUX
Digital System Routing I/F
Digital System Routing I/F
IRQs
DRQs
UDB ARRAY
Del-Sig
Controller
Interrupt
SC/CT
Blocks
Detect
Detect
Edge
Edge
Controller
DMA
DACs
0
1
0
2
1
2
3
IO Port
Pins
DMA termout (IRQs)
Comparators
Controller
Controller
Interrupt
Clocks
DMA
Global
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the system clock (see
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-15. I/O Pin Synchronization Routing
Figure 7-16. I/O Pin Output Connectivity
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
Figure 7-17. I/O Pin Output Enable Connectivity
DO
4 IO Control Signal Connections from
DI
PIN 0
UDB Array Digital System Interface
DO
PIN 0
8 IO Data Output Connections from the
OE
UDB Array Digital System Interface
PIN1
DO
PIN1
OE
PIN2
DO
PIN2
OE
PSoC
Figure
PIN3
DO
PIN3
OE
Port i
Port i
6-1). Normally all inputs from pins
PIN4
®
DO
PIN4
OE
3: CY8C38 Family
PIN5
DO
PIN5
OE
PIN6
DO
Data Sheet
PIN6
OE
Page 47 of 129
PIN7
DO
PIN7
OE
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