EVAL-AD5252EBZ Analog Devices Inc, EVAL-AD5252EBZ Datasheet - Page 7

• Manufacturer Part Number: EVAL-AD5252EBZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5252EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: AD5252
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERFACE TIMING CHARACTERISTICS
All input control voltages are specified with t
characteristics are measured using both V
Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts)
Parameter
INTERFACE TIMING
FLASH/EE MEMORY RELIABILITY
1
2
3
4
Guaranteed by design; not subject to production test. See Figure 23 for location of measured values.
During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM data restoring time, whereas RDAC3 has the longest.
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
Retention lifetime equivalent at junction temperature T
with junction temperature in Flash/EE memory.
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
EEMEM Data Storing Time
EEMEM Data Restoring Time at Power-On
EEMEM Data Restoring Time upon Restore
EEMEM Data Rewritable Time (Delay Time
Endurance
Data Retention
F
R
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
Fall Time of Both SDA and SCL Signals
Rise Time of Both SDA and SCL Signals
Command or Reset Operation
After Power-On or Reset Before EEMEM
Can Be Written)
Bus-Free Time Between Stop and Start
Low Period of SCL Clock
High Period of SCL Clock
Set-up Time for Start Condition
Hold Time (Repeated Start)
Data Set-up Time
Set-up Time for Stop Condition
Data Hold Time
3
4
2
DD
2
= 3 V and 5 V.
R
= t
J
= 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCL
1
2
3
4
5
6
7
8
9
10
EEMEM_STORE
EEMEM_RESTORE1
EEMEM_RESTORE2
EEMEM_REWRITE
Rev. B | Page 7 of 28
Conditions
After this period, the first clock pulse is
generated.
V
without decoupling capacitors at V
and V
V
DD
DD
rise time dependent. Measure
= 5 V.
SS
.
1
DD
Min
1.3
0.6
1.3
0.6
0.6
0
100
0.6
100
AD5251/AD5252
Typ
26
300
300
540
100
Max
400
0.9
300
300
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
ms
μs
μs
μs
k cycles
Years