EVAL-AD5254EBZ Analog Devices Inc, EVAL-AD5254EBZ Datasheet - Page 7

• Manufacturer Part Number: EVAL-AD5254EBZ
• Description: Evaluation Board
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5254EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: AD5245
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTERFACE TIMING CHARACTERISTICS
All input control voltages are specified with t
characteristics are measured using both V
Table 3.
Parameter
INTERFACE TIMING
FLASH/EE MEMORY RELIABILITY
1
2
3
4
5
6
7
See Figure 23 for location of measured values.
Typical values represent average readings at 25°C and V
During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM restore time, whereas RDAC3 has the longest.
Delay time after power-on or reset before new EEMEM data to be written.
Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.
Retention lifetime equivalent at junction temperature T
with junction temperature.
When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the I
about 0.8 mA at V
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
EEMEM Data Storing Time
EEMEM Data Restoring Time at Power-On
EEMEM Data Restoring Time upon Restore
EEMEM Data Rewritable Time
Endurance
Data Retention
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
SU;STO
Fall Time of Both SDA and SCL Signals
Rise Time of Both SDA and SCL Signals
Command or Reset Operation
Bus-Free Time Between Stop and Start
Low Period of SCL Clock
High Period of SCL Clock
Set-up Time for Start Condition
Hold Time (Repeated Start)
Data Set-up Time
Set-up Time for Stop Condition
Data Hold Time
1
5
DD
6, 7
= 5.5 V and 0.2 mA at V
4
3
DD
= 2.7 V.
DD
3
= 3 V and 5 V.
R
= t
J
DD
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
= 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates
SCL
1
2
3
4
5
6
7
8
9
10
EEMEM_STORE
EEMEM_RESTORE1
EEMEM_RESTORE2
EEMEM_REWRITE
= 5 V.
F
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching
Rev. B | Page 7 of 32
Conditions
After this period, the first clock pulse is
generated.
V
decoupling capacitors at V
V
DD
DD
rise time dependent. Measure without
= 5 V.
DD
and V
2
SS
C interface at these pins conducts a current of
.
Min
1.3
0.6
1.3
0.6
0.6
0
100
0.6
100
AD5253/AD5254
Typ
26
300
300
540
100
2
Max
400
0.9
300
300
Unit
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
ms
μs
μs
μs
K cycles
Years