EVAL-AD5270SDZ Analog Devices Inc, EVAL-AD5270SDZ Datasheet - Page 10

• Manufacturer Part Number: EVAL-AD5270SDZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5270SDZ

• Main Purpose: Digital Potentiometer
• Embedded: No
• Utilized Ic / Part: AD5270
• Primary Attributes: 1 Channel, 1024 Position
• Secondary Attributes: 2.7 ~ 5.5 V, 5 ppm/°C, SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5270/AD5271
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 10. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
EPAD
Mnemonic
V
A
W
V
EXT_CAP
GND
SDO
DIN
SCLK
SYNC
Exposed Pad
DD
SS
EXT_CAP
Figure 5. MSOP Pin Configuration
V
V
DD
SS
W
A
1
1
2
2
3
3
4
4
5
(Not to Scale)
AD5270/
AD5271
TOP VIEW
Description
Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors.
Terminal A of RDAC. V
Wiper Terminal of RDAC. V
Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic
capacitors and 10 μF capacitors.
External Capacitor. Connect a 1 μF capacitor between EXT_CAP and V
rating of ≥7 V.
Ground Pin, Logic Ground Reference.
Serial Data Output. This pin can be used to clock data from the shift register in daisy-chain mode or in
readback mode. This open-drain output requires an external pull-up resistor even if it is not use.
Serial Data Line. This pin is used in conjunction with the SCLK line to clock data into or out of the 16-bit input
register.
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 50 MHz.
Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the shift register and data is transferred in on the falling edges of the subsequent clocks.
The selected register is updated on the rising edge of SYNC following the 16
high before the 16
ignored by the RDAC.
Leave floating or connected to V
10
9
8
7
6
SYNC
SCLK
DIN
SDO
GND
th
clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is
SS
≤ V
SS
A
≤ V
≤ V
W
Rev. E | Page 10 of 24
DD
SS
≤ V
.
.
DD
.
EXT_CAP
NOTES
1. THE EXPOSED PAD IS LEFT FLOATING
OR IS TIED TO V
V
V
DD
SS
W
Figure 6. LFCSP Pin Configuration
A
1
2
3
4
5
SS
. This capacitor must have a voltage
AD5270/
(EXPOSED
SS
AD5271
.
PAD)
th
clock cycle. If SYNC is taken
10
9
8
7
6 GND
SYNC
SCLK
DIN
SDO