EVAL-AD5292EBZ Analog Devices Inc, EVAL-AD5292EBZ Datasheet - Page 27

• Manufacturer Part Number: EVAL-AD5292EBZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5292EBZ

• Main Purpose: Digital Potentiometer
• Embedded: Yes
• Utilized Ic / Part: AD5292
• Primary Attributes: 1 Channel, 256 Position
• Secondary Attributes: SPI Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operation of the digital potentiometer in the voltage divider
mode results in a more accurate operation over temperature.
Unlike the rheostat mode, the output voltage is dependent
mainly on the ratio of the internal resistors, R
not the absolute values. Therefore, the temperature drift reduces
to 5 ppm/°C.
EXT_CAP CAPACITOR
A 1 μF capacitor to GND must be connected to the EXT_CAP
pin (see Figure 68) on power-up and throughout the operation
of the AD5291 and AD5292.
TERMINAL VOLTAGE OPERATING RANGE
The positive V
AD5291 and AD5292 define the boundary conditions for
proper 3-terminal digital potentiometer operation. Supply
signals present on Terminal A, Terminal B, and Terminal W
that exceed V
biased diodes (see Figure 69).
Figure 69. Maximum Terminal Voltages Set by V
DD
Figure 68. Hardware Setup for EXT_CAP Pin
DD
or V
and negative V
EXT_CAP
1µF
C1
SS
are clamped by the internal forward-
AD5291/
AD5292
MEMORY
SS
BLOCK
GND
OTP
power supplies of the
WA
DD
V
A
W
B
V
and R
DD
SS
and V
WB
SS
, and
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The ground pins of the AD5291 and AD5292 devices are
primarily used as a digital ground reference. To minimize the
digital ground bounce, the AD5291 and AD5292 ground
terminals should be joined remotely to the common ground.
The digital input control signals to the AD5291 and AD5292
must be referenced to the device ground pin (GND), and satisfy
the logic level defined in the Specifications section.
Power-Up Sequence
To ensure that the AD5291 and AD5292 power up correctly, a
1 μF capacitor must be connected to the EXT_CAP pin. Because
there are diodes to limit the voltage compliance at Terminal A,
Terminal B, and Terminal W (see Figure 69), it is important to
power V
Terminal B, and Terminal W. Otherwise, the diode is forward-
biased such that V
The ideal power-up sequence is GND, V
digital inputs, and then V
up V
they are powered after V
Regardless of the power-up sequence and the ramp rates of the
power supplies, after V
activates, restoring the 20-TP memory value to the RDAC register.
A
, V
DD
B
, V
and V
W
, and the digital inputs is not important as long as
SS
DD
first before applying any voltage to Terminal A,
and V
LOGIC
DD
A
, V
, V
SS
is powered, the power-on preset
are powered up unintentionally.
B
SS
, and V
, and V
W
LOGIC
AD5291/AD5292
. The order of powering
SS
, V
.
LOGIC
and V
DD
, the