EVAL-AD7401AEDZ Analog Devices Inc, EVAL-AD7401AEDZ Datasheet - Page 17

• Manufacturer Part Number: EVAL-AD7401AEDZ
• Description: EVALUATION BOARD I.C.
• Manufacturer: Analog Devices Inc
• Series: iCoupler®r

Specifications of EVAL-AD7401AEDZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 20M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±320 mV
• Power (typ) @ Conditions: 105mW @ 20MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Utilized Ic / Part: AD7401A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Z = one sample delay
MCLKOUT = modulators conversion bit rate
*/
always @ (posedge mclk1 or posedge reset)
if (reset)
else
/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)
*/
always @ (negedge mclk1 or posedge reset)
if (reset)
else
always @ (word_count)
/*DIFFERENTIATOR ( including decimation
stage)
Perform the differentiation stage (FIR) at a
lower speed.
WORD_CLK
ACC3
begin
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
begin
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
/*initialize acc registers on reset*/
/*perform accumulation process*/
word_count <= 0;
word_count <= word_count + 1;
word_clk <= word_count[7];
Z
–1
Figure 28. Differentiator
+
–
DIFF1
Z
–1
–
+
–
DIFF2
Z
–1
+
–
DIFF3
Rev. B | Page 17 of 20
Z = one sample delay
WORD_CLK = output word rate
*/
always @ (posedge word_clk or posedge reset)
if(reset)
else
/* Clock the Sinc output into an output
register
WORD_CLK = output word rate
*/
always @ (posedge word_clk)
begin
DATA[15] <= diff3[23];
DATA[14] <= diff3[22];
DATA[13] <= diff3[21];
DATA[12] <= diff3[20];
DATA[11] <= diff3[19];
DATA[10] <= diff3[18];
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
end
endmodule
begin
acc3_d2 <= 0;
diff1_d <= 0;
diff2_d <= 0;
diff1 <= 0;
diff2 <= 0;
diff3 <= 0;
end
begin
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end
Figure 29. Clocking Sinc Output into an Output Register
<= diff3[17];
<= diff3[16];
<= diff3[15];
<= diff3[14];
<= diff3[13];
<= diff3[12];
<= diff3[11];
<= diff3[10];
<= diff3[9];
<= diff3[8];
WORD_CLK
DIFF3
DATA
AD7401A