EVAL-ADAU1446EBZ Analog Devices Inc, EVAL-ADAU1446EBZ Datasheet - Page 48

• Manufacturer Part Number: EVAL-ADAU1446EBZ
• Description: Evaluation BD 175MHZ SigmaDSP,8x2 SRCs
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r

Specifications of EVAL-ADAU1446EBZ

• Main Purpose: Audio, Audio Processing
• Embedded: Yes, DSP
• Utilized Ic / Part: ADAU1446
• Primary Attributes: 28/56-bit, Audio DSP, Single-chip, Multichannel
• Secondary Attributes: I²C & SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1445/ADAU1446
Sample Rate Conversion Before the DSP
If asynchronous input signals are present in the system, they
must be routed through the ASRC before being processed by
the DSP. This is made possible by routing the asynchronous
signals through the input side of the routing matrix to the
ASRC inputs. This is illustrated in Figure 43.
In such a situation, the ASRC target sample rate should be set
synchronous to the DSP. After conversion, the signals are
passed to the DSP and are then available in SigmaStudio in the
ASRC input cell.
Sample Rate Conversion After the DSP
After processing signals in the DSP, it is sometimes desirable to
output them asynchronous to the DSP rate, for example, when
an asynchronous external DAC is in the system. This can be
accomplished by routing the signals through the input side of
the routing matrix from the DSP-to-ASRC pairs to the ASRC
inputs. This is illustrated in Figure 44.
In this situation, the ASRC target sample rate can be set to any
desired value, and the audio data is sent to the output side of the
routing matrix.
DSP Inputs and Outputs
In the DSP, the signals are represented as input and output blocks
within the SigmaStudio development tool and then undergo
processing as determined by the SigmaStudio schematic. There
are 21 input and output channel pairs, as shown in Figure 45. In
FROM SERIAL
INPUT PORTS
FROM SERIAL
INPUT PORTS
Figure 44. Routing DSP Outputs to Asynchronous Output Signals
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
S/PDIF Rx
Figure 43. Routing Asynchronous Input Signals to DSP Inputs
0, 1
2, 3
4, 5
6, 7
8, 9
FROM
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
0, 1
2, 3
4, 5
6, 7
8, 9
FARM
FROM DSP
FARM
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
(8 × 2 CH)
STEREO
ASRCs
(8 × 2 CH)
STEREO
ASRCs
10, 11
12, 13
14, 15
0, 1
2, 3
6, 7
8, 9
4, 5
8
RATE
10, 11
12, 13
14, 15
0, 1
2, 3
6, 7
8, 9
4, 5
8
TO DSP
TO FARM
(OUTPUT SIDE)
RATE
Rev. A | Page 48 of 92
SigmaStudio, each pair is accessible as individual channels and,
therefore, does not need to remain as a pair.
Some algorithms running inside the SigmaStudio signal flow
may mix or split channels within the DSP. Therefore, the
number of output pairs does not necessarily have to equal the
number of input pairs.
Note that, while the S/PDIF Rx pair can be routed either to the
FARM input side or directly to the DSP, the S/PDIF Tx pair
must be routed directly to the S/PDIF output pin (SPDIFO),
bypassing the FARM output side.
The ASRC I/O block in Figure 45 represents the interaction
between the DSP and the ASRCs. Inputs to the DSP from the
ASRCs (ASRC-to-DSP pairs) are represented in SigmaStudio as
ASRC input cells, whereas outputs to the ASRCs from the DSP
(DSP-to-ASRC pairs) are represented in SigmaStudio as ASRC
output cells. The cells are shown in their respective locations in
Figure 46.
SPDIFI
CHANNELS
INPUT
FROM
S/PDIF Rx
Figure 45. DSP Core Input and Output Signals
10, 11
12, 13
14, 15
Figure 46. ASRC Input and Output Cells
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
0, 1
2, 3
4, 5
6, 7
8, 9
0, 1
2, 3
4, 5
6, 7
8, 9
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
SERIAL I/O
DSP CORE
S/PDIF I/O
ASRC I/O
(24 CH)
(16 CH)
(2 CH)
ASRC I/O
(16 CH)
10, 11
12, 13
14, 15
0, 1
2, 3
6, 7
8, 9
4, 5
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
0, 1
2, 3
4, 5
6, 7
8, 9
S/PDIF Tx
10, 11
12, 13
14, 15
0, 1
2, 3
4, 5
6, 7
8, 9
TO FARM
(OUTPUT SIDE)
SPDIFO