WM8805GEDS Wolfson Microelectronics, WM8805GEDS Datasheet - Page 21

Audio Transmitters, Receivers, Transceivers 8:1 Digi. Interface Transcvr with PLL

WM8805GEDS

Manufacturer Part Number
WM8805GEDS
Description
Audio Transmitters, Receivers, Transceivers 8:1 Digi. Interface Transcvr with PLL
Manufacturer
Wolfson Microelectronics
Datasheet

Specifications of WM8805GEDS

Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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MASTER CLOCK AND PHASE LOCKED LOOP
SOFTWARE MODE INTERNAL CLOCKING
w
Production Data
The WM8805 is equipped with a comprehensive clocking scheme that provides maximum flexibility
and function and many configurable routing possibilities for the user in software mode. An overview
of the software mode clocking scheme is shown in Figure 16.
Figure 16 Software Mode Clocking Scheme Overview
The clocking scheme can be divided into four sections. These are detailed as follows:
OSCILLATOR
The primary function of the oscillator is to generate the oscillator clock (OSCCLK) for the PLL input.
Whenever the PLL or the S/PDIF receiver is enabled, the oscillator must be used to generate the
OSCCLK signal for the PLL.
The secondary function of the oscillator is to generate the OSCCLK so that it can be selected
internally as the clock source for:
The oscillator has one control bit as shown in Table 19. The oscillator must be powered up to
generate the OSCCLK signal.
Table 19 Oscillator Control
REGISTER
ADDRESS
PWRDN
R30
1Eh
The MCLK output pin, when the pin is configured as an output.
The CLKOUT output pin, when enabled.
BIT
3
LABEL
OSCPD
DEFAULT
1
Oscillator Power Down Control
0 = Power up
1 = Power down
DESCRIPTION
PD Rev 4.1 September 07
WM8805
21

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