WM8805GEDS Wolfson Microelectronics, WM8805GEDS Datasheet - Page 38

• Manufacturer Part Number: WM8805GEDS
• Description: Audio Transmitters, Receivers, Transceivers 8:1 Digi. Interface Transcvr with PLL
• Manufacturer: Wolfson Microelectronics

Specifications of WM8805GEDS

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8805
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Table 43 S/PDIF Receiver Channel Status Register 4
Table 44 S/PDIF Receiver Channel Status Register 5
Note 1:
interface transmitted data. Truncation replaces the lower data bits with 0. Truncation can be masked using
the WL_MASK control bit. Truncation can be masked by the WL_MASK. Refer to received channel status bit
description
REGISTER
REGISTER
ADDRESS
RXCHAN4
(read-only)
ADDRESS
RXCHAN5
(read-only)
R16
R17
10h
11h
MAXWL and RXWL[2:0] bits in recovered channel status data are used to truncate digital audio
BIT
BIT
3:0
5:4
3:1
7:4
0
CLKACU[1:0]
ORGSAMP
RXWL[2:0]
FREQ[3:0]
MAXWL
LABEL
LABEL
[3:0]
CHANNEL
CHANNEL
STATUS
STATUS
27:24
29:28
35:33
39:36
BIT
BIT
32
DEFAULT
DEFAULT
0001
0000
000
11
1
Indicated Sampling Frequency
Refer to S/PDIF specification (IEC 60958-3)
for full details.
Clock Accuracy of Received Clock
00 = Level II
01 = Level I
10 = Level III
11 = Interface frame rate not matched to
sampling frequency.
Maximum Audio Sample Word Length
0 = 20 bits
1 = 24 bits
Note: see table in description of bits 3:1 of
this register,
Audio Sample Word Length
000: Word Length Not Indicated
All other combinations are reserved and may
give erroneous operation. Data will be
truncated internally when these bits are set
unless WL_MASK is set. See note 1.
Original Sampling Frequency
Refer to S/PDIF specification (IEC 60958-3)
for full details.
RXWL[2:0]
001
010
100
101
110
DESCRIPTION
DESCRIPTION
MAXWL==1
20 bits
22 bits
23 bits
24 bits
21 bits
PD Rev 4.1 September 07
Production Data
MAXWL==0
16 bits
18 bits
19 bits
20 bits
17 bits
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