COM20020I3V-HT SMSC, COM20020I3V-HT Datasheet - Page 34

• Manufacturer Part Number: COM20020I3V-HT
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20020I3V-HT

• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 35 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SMSC COM20020I 3.3V Rev.E
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
BIT
6,5
7
4
3
2
Read Bus Timing
Select
Reserved
Clock Multiplier
Enhanced
Functions
No Synchronous
BIT NAME
RBUSTMG This bit is used to Disable/Enable the High Speed CPU
CKUP
EF
NOSYNC
SYMBOL
Table 12 - SETUP 2 REGISTER
DATASHEET
Read function for High Speed CPU bus support.
RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable.
That is, if BUSTMG (pin 26: Only for TQFP package) = 1
and RBUSTMG = 1, High Speed CPU Read operations are
enabled.
It does not influence write operation.
Read operation is only for non-multiplexed bus.
These bits are undefined. They must be 0.
Higher frequency clocks are generated from the 20 MHz
crystal through the selection of these two bits as shown.
This clock multiplier is powered-down on default. After
changing the CKUP bit, the ARCNET core operation is
stopped and the internal PLL in the clock multiplier is
awakened and it starts to generate the 40 MHz. The lock out
time of the internal PLL is 8μSec typically. After 1 mS it is
necessary to write command data '18H' to command
register for re-starting the ARCNET core operation.
CAUTION: Changing the CKUP bit must be one time or less
after releasing a hardware reset.
Note: After changing the CKUP bit, it is necessary to write a
command data '18H' to the command register. Because
after changing the CKUP bits, the internal operation is
stopped temporarily. The writing of the command is to start
the operation.
These initializing steps are shown below.
This bit is used to enable the new enhanced functions in the
COM20020I 3V. EF = 0: Disable (Default), EF = 1: Enable. If
EF = 0, the timing and function is the same as in the
COM20020I, Revision B. See appendix “A”. EF bit must
be ‘1’ if the data rate is over 5Mbps.
EF bit should be ‘1’ for new design customers.
EF bit should be ‘0’ for replacement customers.
This bit is used to enable the SYNC command during
initialization. NOSYNC= 0, Enable (Default) The line must
be idle for the RAM initialization sequence to be written.
NOSYNC= 1, Disable:) The line does not have to be idle for
the RAM initialization sequence to be written. See appendix
“A”.
CKUP
0
1
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Clock Frequency (Data Rate)
20 MHz (Up to 2.5Mbps) Default
40 MHz (Up to 5Mbps)
Hardware reset (Power ON)
Change CKUP bit
Wait 1mSec (wait until stable oscillation)
Write command '18H' (start internal
operation)
Start initializing routine (Execute existing
software)
DESCRIPTION
High speed CPU
Revision 09-11-06