COM20020I-HD SMSC, COM20020I-HD Datasheet
COM20020I-HD
Specifications of COM20020I-HD
Related parts for COM20020I-HD
COM20020I-HD Summary of contents
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... On-Chip Dual Port RAM Command Chaining for Packet Queuing Sequential Access to Internal RAM Software Programmable Node ID COM20020I 3V-DZD for 28 pin PLCC * Lead-Free RoHS Compliant package COM20020I 3V-HT for 48 pin TQFP Lead-Free RoHS Compliant package * TQFP package is recommended for new design SMSC COM20020I 3.3V Rev.E COM20020I 3 ...
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... OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC COM20020I 3.3V Rev.E Page 2 DATASHEET ...
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... OPERATIONAL DESCRIPTION .....................................................................................................45 7 AXIMUM UARANTEED ATINGS 7 LECTRICAL HARACTERISTICS CHAPTER 8 TIMING DIAGRAMS .......................................................................................................................48 CHAPTER 9 PACKAGE OUTLINES ...................................................................................................................63 CHAPTER 10 APPENDIX A...................................................................................................................................65 CHAPTER 11 APPENDIX B...................................................................................................................................68 CHAPTER 12 APPENDIX C...................................................................................................................................69 12 OFTWARE DENTIFICATION OF THE SMSC COM20020I 3.3V Rev.E TABLE OF CONTENTS ........................................................................................................................12 ......................................................................................................................12 .....................................................................................................................15 ..................................................................................................................19 * .................................................................................................................45 ................................................................................................................45 COM20020I ............................................................69 EV AND EV Page 3 DATASHEET Revision 09-11-06 ...
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... Figure 2 - Multiplexed, 8051-Like Bus Interface With RS-485 Interface.......................................................................16 Figure 3 - Non-Multiplexed, 6801-Like Bus Interface With RS-485 Interface ...............................................................17 Figure 4 - High Speed Cpu Bus Timing - Intel CPU Mode ...........................................................................................18 Figure 5 - COM20020I 3V Network Using RS-485 Differential Transceivers..................................................................20 Figure 6 - Dipulse Waveform For Data Of 1-1-0...........................................................................................................20 Figure 7 - Internal Block Diagram.................................................................................................................................22 Figure 8 – ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM Chapter 1 General Description SMSC's COM20020I member of the family of Embedded ARCNET Controllers from Standard Microsystems Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent peripherals in industrial and embedded control environments using an ARCNET protocol engine. The flexible microcontroller and media interfaces, eight-page message support, and extended temperature range of the COM20020I 3V make it the only true network controller optimized for use in industrial and embedded applications ...
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... PACKAGE TYPE Plastic, LJP = PLCC PACKAGE TYPE Plastic, LJP = PLCC COM20020I 3V P TEMP RANGE: TEMP RANGE Industrial: -40° 75° C DEVICE TYPE: 20020 = Universal Local Area Network DEVICE TYPE: 20019 = Universal Local Area Network Controller RAM) SMSC COM20020I 3.3V Rev nWR/DIR 26 27 ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM AD0 1 AD1 2 N/C 3 AD2 4 N/C 5 VSS VDD VSS SMSC COM20020I 3.3V Rev.E COM20020I COM20020I 3V 48 PIN TQFP 48 PIN TQFP NOTE: BUSTMG pin is only TQFP package Page 7 DATASHEET 36 nCS 35 VDD 34 nINTR 33 N/C 32 VDD 31 nRESET 30 VSS 29 nTXEN 28 ...
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... Select - 26 Read/Write Bus Timing Select SMSC COM20020I 3.3V Rev.E SYMBOL I/O MICROCONTROLLER INTERFACE On a non-multiplexed mode, A0-A2 are address A0/nMUX IN input bits. (A0 is the LSB multiplexed A1 IN address/data bus, nMUX tied Low left open, and ALE is tied to the Address Latch Enable signal. ...
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... N/C 14-17, 19, 27, 33, 35, 38, 40, 42, 47, 48 SMSC COM20020I 3.3V Rev.E SYMBOL I/O TRANSMISSION MEDIA INTERFACE In Normal Mode, these active low signals carry the nPULSE1 OUT transmit data information, encoded in pulse format as DIPULSE waveform. In Backplane Mode, the nPULSE1 signal driver is programmable (push/pull ...
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... Packet Pass the Token CRC No OK? Increment Y N Activity NID Y for 37.4 us? LENGTH OK? Y DID =0? N DID =ID? Y SEND ACK Figure 1 - COM20020I 3V Operation Page 10 DATASHEET Activity for 41 uS Set NID=ID N Broadcast Enabled? Start Timer: Y T=(255-ID Activity Y On Line T=0? ...
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... ACKnowledge message (or nothing not received successfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful delivery of the packet. An interrupt mask permits the COM20020I 3V to generate an interrupt to the processor when selected status bits become true. Figure flow chart illustrating the internal operation of the COM20020I 3V connected MHz crystal oscillator. ...
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... NETWORK RECONFIGURATION, INVITATIONS TO TRANSMIT are sent to all NIDs (1-255). Each COM20020I 3V on the network will finally have saved a NID value equal to the ID of the COM20020I 3V that it released control to. At this point, control is passed directly from one node to the next with no wasted INVITATIONS TO TRANSMIT being sent to ID's not on the network, until the next NETWORK RECONFIGURATION occurs ...
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... The logic levels on these bits control the maximum distances over which the COM20020I 3V can operate by controlling the three timeout values described above. For proper network operation, all COM20020I 3V's connected to the same network must have the same Response Time, Idle Time, and Reconfiguration Time. ...
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... ALERT BURST ACK Negative Acknowledgements A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII code 15H) character ALERT BURST NAK SMSC COM20020I 3.3V Rev.E DID COUNT data data Page 14 DATASHEET 16 15 ...
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... READY inputs, standard peripherals cannot extend cycles to extend the access time. The access time of the COM20020I 3V, on the other hand fast that it does not need to limit the speed of the microcontroller. The COM20020I 3V is designed to be flexible so that it is independent of the microcontroller speed. ...
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... A15 RESET nRD nWR nINT1 8051 RXIN TXEN nPULSE1 nPULSE2 GND BACKPLANE CONFIGURATION FIGURE A Figure 2 - Multiplexed, 8051-Like Bus Interface With RS-485 Interface SMSC COM20020I 3.3V Rev.E COM20022 AD0-AD2, D3-D7 A2/BALE RXIN nCS 75176B or nRESET nTXEN Equiv. nPULSE1 nRD/nDS nPULSE2 nWR/DIR GND ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM XTAL1 XTAL2 D0- nRES nIOS R/nW nIRQ1 6801 RXIN nTXEN nPULSE1 nPULSE2 Figure 3 - Non-Multiplexed, 6801-Like Bus Interface With RS-485 Interface SMSC COM20020I 3.3V Rev.E COM20022 D0-D7 A0/nMUX A1 A2/BALE nCS nPULSE1 nRESET nPULSE2 nRD/nDS nWR/nDIR nINTR 27 pF +5V HYC9068 or 10 HYC9088 ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM High Speed CPU Bus Timing Support High speed CPU bus support was added to the COM20020I 3V. The reasoning behind this is as follows: With the Host interface in Non-multiplexed Bus mode, I/O address and Chip Select signals must be stable before the read signal is active and remain after the read signal is inactive ...
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... RF transformer of the LAN Driver, which produces a positive pulse at the RXIN pin of the COM20020I 3V. The pulse on the RXIN pin represents a logic "1". Lack of pulse represents a logic "0". Typically, RXIN pulses occur at multiples of 400nS. The COM20020I 3V can tolerate distortion of plus or minus 100nS and still correctly capture and convert the RXIN pulses to NRZ format ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM RT 75176B or Equiv. COM20022I 3V Figure 5 - COM20020I 3V Network Using RS-485 Differential Transceivers 20MHZ CLOCK (FOR REF. ONLY) 100ns nPULSE1 nPULSE2 200ns DIPULSE RXIN Figure 6 - Dipulse Waveform For Data Of 1-1-0 SMSC COM20020I 3.3V Rev.E +VCC +VCC ...
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... COM20020I 3V. The nPULSE1 signal transmits the data, provided the Transmit Enable signal is active. The nPULSE1 signal issues a 200nS (at 2.5Mbps) negative pulse to transmit a logic "1". Lack of pulse indicates a logic "0". The RXIN signal receives the data, the transmitter portion of the COM20020I 3V is disabled during reset and the nPULSE1, nPULSE2 and nTXEN pins are inactive. ...
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... ADDRESS DECODING CIRCUITRY AD0-AD2, D3-D7 STATUS/ nINTR COMMAND REGISTER RESET nRESET LOGIC nRD/nDS nWR/DIR BUS ARBITRATION nCS CIRCUITRY SMSC COM20020I 3.3V Rev RAM MICRO- SEQUENCER AND WORKING REGISTERS OSCILLATOR RECONFIGURATION NODE ID LOGIC TIMER Figure 7 - Internal Block Diagram Page 22 DATASHEET ADDITIONAL REGISTERS ...
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... Note: For more detailed information on Cabling options including RS-485, transformer-coupled RS-485 and Fiber Optic interfaces, please refer to TN7-5 – Cabling Guidelines for the COM20020I 3V ULANC, available from Standard Microsystems Corporation. SMSC COM20020I 3.3V Rev.E ...
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... The COM20020I 3V derives a 10 MHz and a 5 MHz clock from the output clock of the Clock Multiplier. These clocks provide the rate at which the instructions are executed within the COM20020I 3V. The 10 MHz clock is the rate at which the program counter operates, while the 5 MHz clock is the rate at which the instructions are executed ...
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... Interrupt Mask Register (IMR) The COM20020I 3V is capable of generating an interrupt signal when certain status bits become true. A write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic " ...
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... ID bit of the Diagnostic Status Register helps the user find a unique Node ID. Refer to the Initialization Sequence section for further detail on the use of the DUPID bit. The core of the COM20020I 3V does not wake up until a Node ID other than zero is written into the Node ID Register. During this time, no microcode is executed, no tokens are passed by this node, and no reconfigurations are caused by this node ...
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... Disable/Enable Fast Read function for High Speed CPU bus support. The EF bit is used to enable the new timing for certain functions in the COM20020I 3V ( the timing is the same as in the COM20020I 3V Rev. B). See Appendix “A”. The NOSYNC bit is used to enable the NOSYNC function during initialization. If this bit is reset, the line has to be idle for the RAM initialization sequence to be written. If set, the line does not have to be idle for the initialization sequence to be written. See Appendix “ ...
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... NAK. These bits are undefined. This bit, if high, indicates that the COM20020I 3V has been reset by either a software reset, a hardware reset, or writing 00H to the Node ID Register. The POR bit is cleared by the "Clear Flags" ...
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... New Next ID NEW NXTID 0 (Reserved) SMSC COM20020I 3.3V Rev.E DESCRIPTION This bit, if high, indicates that a past reconfiguration was caused by this node set when the Lost Token Timer times out, and should be typically read following an interrupt caused by RECON. Refer to the Improved Diagnostics section for further detail. ...
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... If "c" logic "0", the device handles only short packets. This command resets certain status bits of the COM20020I 3V. A logic "1" on "p" resets the POR status bit and the EXCNAK Diagnostic status bit. A logic "1" on "r" resets the RECON status bit ...
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... Table 10 - Configuration Register SYMBOL DESCRIPTION RESET A software reset of the COM20020I 3V is executed by writing a logic "1" to this bit. A software reset does not reset the microcontroller interface mode, nor does it affect the Configuration Register. The only registers that the software reset affect are the Status Register, the Next ID Register, and the Diagnostic Status Register. back to logic " ...
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... These bits allow the network to operate over longer distances than the default maximum 2 miles by controlling the Response, Idle, and Reconfiguration Times. should be configured with the same timeout values for proper network operation. For the COM20020I 3V with a 20 MHz crystal oscillator, the bit combinations follow: ET2 ET1 ...
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... Note that ACKs are only sent for packets received with a destination ID equal to the COM20020I 3V's programmed node ID. This feature can be used to put the COM20020I 'listen-only' mode, where the transmitter is disabled and the COM20020I 3V is not passing tokens. Defaults low. ...
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... Start initializing routine (Execute existing software) EF This bit is used to enable the new enhanced functions in the COM20020I 3V Disable (Default Enable the timing and function is the same as in the COM20020I, Revision B. See appendix “A”. EF bit must be ‘1’ if the data rate is over 5Mbps. ...
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... Internal Ram The integration of the RAM in the COM20020I 3V represents significant real estate savings. The most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the integration of RAM). In addition, the PC board is now free of the cumbersome external RAM, external latch, and multiplexed address/data bus and control functions which were necessary to interface to the RAM ...
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... Access Speed The COM20020I 3V is able to accommodate very fast access cycles to its registers and buffers. Arbitration to the buffer does not slow down the cycle because the pointer based access method allows data to be prefetched from memory and stored in a temporary register ...
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... Please note that it is the responsibility of software to reserve 512 bytes for each receive page if the device is configured to handle long packets. The COM20020I 3V does not check page boundaries during reception. If the device is configured to handle only short packets, then both transmit and receive pages may be allocated as 256 bytes long, freeing at least 1KByte at any given time ...
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... FOR BROADCASTS) Figure 9 – Ram Buffer Packet Configuration The SID in Address 0 is used by the receiving node to reply to the transmitting node. The COM20020I 3V puts the local ID in this location, therefore it is not necessary to write into this location. Please note that a short packet may contain between 1 and 253 data bytes, while a long packet may contain between 257 and 508 data bytes ...
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... In the latter case, Address 3 contains the value 512-N, where N represents the message length. Note that on reception, the COM20020I 3V deposits packets into the RAM buffer in the same format that the transmitting node arranges them, which allows for a message to be received and then retransmitted without rearranging any bytes in the RAM buffer other than the SID and DID. Once the packet is received and stored correctly in the selected buffer, the COM20020I 3V sets the RI bit to logic " ...
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... Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status bits, are pipelined. In order for the COM20020I compatible with previous SMSC ARCNET device drivers, the device defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the Command Chaining Mode must be enabled via a logic " ...
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... In the COM20020I 3V, the Receive Inhibit (RI) bit of the Interrupt Mask Register now masks only the TRI bit of the Status Register, not the RI bit as in the non-chaining mode. Since the TRI bit is only set upon reception of a packet (not by RESET), and since the TRI bit may easily be reset by issuing a " ...
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... Diagnostic Status Register is set after a maximum of 420mS (or 840mS if the ET1 and ET2 bits are other than 1,1). To determine if another node on the network already has this ID, the COM20020I 3V compares the value in the Node ID Register with the DID's of the token, and determines whether there is a response to it. Once the Diagnostic Status Register is read, the DUPID bit is cleared ...
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... If an external crystal is used, two capacitors are needed (one from each leg of the crystal to ground). No external resistor is required, since the COM20020I 3V contains an internal resistor. The crystal must have an accuracy of 0.020% SMSC COM20020I 3.3V Rev.E No receive activity is seen and the basic transmit function is enabled. ...
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... The XTAL2 side of the crystal may be loaded with a single 74HC-type buffer in order to generate a clock for other devices. The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a 390Ω pull-up resistor is required on XTAL1, while XTAL2 should be left unconnected. SMSC COM20020I 3.3V Rev.E Page 44 DATASHEET Revision 09-11-06 ...
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... D3-D7, nINTR, nPULSE1 in Push/Pull Mode, nPULSE2) High Output Voltage 2 (AD0-AD2, D3-D7, nINTR, nPULSE1 in Push/Pull Mode, nPULSE2) Low Output Voltage 3 (nPULSE1 in Open-Drain Mode) Dynamic V Supply DD Current SMSC COM20020I 3.3V Rev.E SYMBOL MIN TYP MAX V -0.3 0.8 IL1 V 2.0 5.5 IH1 V -0.3 0.2xV IL2 V ...
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... A1, AD0-AD2, D3-D7, XTAL1, BUSTMG) CAPACITANCE (T = 25° 1MHz Output and I/O pins capacitive load specified as follows: PARAMETER SYMBOL Input Capacitance Output Capacitance 1 (All outputs except XTAL2) SMSC COM20020I 3.3V Rev.E SYMBOL MIN TYP MAX I 80 200 P I ± 0V) DD MIN ...
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... Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin. Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0". SMSC COM20020I 3.3V Rev.E Outputs: t 2.0V 0.8V 2.0V 0.8V ...
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... COM20020 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 11 - Multiplexed Bus, 68xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID DATA VALID t1 t2, t4 ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 12 - Multiplexed Bus, 80xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID DATA VALID t1 t2 ...
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... Write cycle for Address Pointer Low Register occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 13 - Multiplexed Bus, 68xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID DATA VALID t2 t12 ...
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... Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 14 - Multiplexed Bus, 80xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID DATA t2, t4 t10 t5 ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 15 - Non-Multiplexed Bus, 80xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID t1 t3 Note 3 t5 ...
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... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 16 - Non-Multiplexed Bus, 80xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID t1 t3 Note 3 t5 ...
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... COM20020 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 17 - Non-Multiplexed Bus, 68xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID ...
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... COM20020 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 18 - Non-Multiplexed Bus, 68xx-Like Control Signals; Read Cycle SMSC COM20020I 3.3V Rev.E VALID t10 ...
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... Register requires a minimum of 5T leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 19 - Non-Multiplexed Bus, 80xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID VALID DATA ...
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... Register requires a minimum of 5T leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 20 - Non-Multiplexed Bus, 80xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID VALID DATA ...
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... Any cycle occurring after a write to the Address Pointer Low Register requires a minimum the next nDS. Write cycle for Address Pointer Low Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 21 - Non-Multiplexed Bus, 68xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID t10 t8 ...
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... Any cycle occurring after a write to the Address Pointer Low Register requires a minimum the next nDS. Write cycle for Address Pointer Low Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 22 - Non-Multiplexed Bus, 68xx-Like Control Signals; Write Cycle SMSC COM20020I 3.3V Rev.E VALID t10 t8 ...
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... Beginning of Last Bit Time to nTXEN High t6 RXIN Active Pulse Width t7 RXIN Period t8 RXIN Inactive Pulse Width Note: Use Only 2.5 Mbps Figure 23 – Normal Mode Transmit Or Receive Timing SMSC COM20020I 3.3V Rev (These signals are to and from the hybrid) Page 60 DATASHEET ...
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... *t3, t11 = ** +/- **t13 = x T +/- Figure 24 – Backplane Mode Transmit or Receive Timing (THESE SIGNALS ARE TO AND FROM THE DIFFERENTIAL DRIVER OR THE CABLE) SMSC COM20020I 3.3V Rev t10 t12 t11 Parameter Page 61 DATASHEET t13 t8 LAST BIT (400 nS BIT TIME) min typ max ...
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... Pulse Width*** t2 nINTR High to Next nINTR Low Note period of external XTAL oscillation frequency. XTL Note**: T is period of Data Rate (i.e. at 2.5 Mbps Note***: When the power is turned on measured from stable XTAL oscillation after V DD SMSC COM20020I 3.3V Rev 1.0V min -200 + - t2 min ...
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... ARCNET (ANSI 878.1) Controller with On-Chip RAM Chapter 9 Package Outlines OTES dim ensions are in inches ircle indicating pin 1 can appear on a top surface as show n on the draw ing or right above beveled edge. Figure Pin PLCC Package Dimensions SMSC COM20020I 3.3V Rev.E PIN 28L ...
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... 0.50 Basic o θ 0.17 R1 0.08 R2 0.08 ccc ~ ccc ~ Note 1: Controlling Unit: millimeter SMSC COM20020I 3.3V Rev.E Figure Pin TQFP Package Outline MAX ~ 1.6 Overall Package Height 0.10 0.15 Standoff 1.40 1.45 Body Thickness 9.00 9.20 X Span 1 4.50 4. Span Measure from Centerline 2 7 ...
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... The following discussion describes the function of this bit: During initialization, after the CPU writes the Node ID, the COM20020I 3V will write "D1"h data to Address 000h and Node-ID to Address 001h of its internal RAM within 6uS. These values are read as part of the diagnostic test. If the D1 and Node-ID initialization sequence cannot be read, the initialization routine will report device diagnostic failure. These writes are controlled by a micro-program which sometimes waits if the line is active ...
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... C) Shorten The Write Interval Time To The Command Register The COM20020I 3V limits the write interval time for continuous writing to the Command register. The minimum interval time is changed by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6 μS at the 156.25 Kbps. This 1.6 μS is very long for CPU ...
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... EF bit. B) Mask Register Reset The Mask register is reset by a soft reset in the COM20020I 3V Rev. A, but is not reset in Rev. B. The Mask register is related to the Status and Diagnostic register should be reset by a soft reset. Otherwise, every time the soft reset happens, the COM20020I 3V Rev. B generates an unnecessary interrupt since the status bits RI and TA are back to one by the soft reset ...
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... SA15-SA4 P 12 SD7-SD0 A 8 nIOR nIOW SA2-SA0 3 IRQm nIOCS16 DRQn nDACK TC nREFRESH RESETDRV Figure 30 - Example Of Interface Circuit Diagram To ISA Bus SMSC COM20020I 3.3V Rev.E LS688x2 12 bit Comparators Q I/O Address Seeting (DIP Switches) P=Q 12 LS245 A 16 bit Bus Transceivers DIR 3 Schmitt-Trigger Buffer ...
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... Chapter 12 Appendix C 12.1 Software Identification of the COM20020I 3V Rev D and Rev E In order to properly write software to work with the COM20020I 3V Rev D and necessary to be able to identify the different revisions of the part. To identify the COM20020I 3V Revision follow the following procedure: 1. Write 0x00 to Register-5 2 ...