COM20020I-HD SMSC, COM20020I-HD Datasheet - Page 51

• Manufacturer Part Number: COM20020I-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20020I-HD

• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SMSC COM20020I 3.3V Rev.E
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
AD0-AD2,
nCS
ALE
nWR
D3-D7
nRD
**
*
PLCC Package: Don’t care RBUSTMG bit, TQFP Package: Must be BUSTMG pin = HIGH
Note 1:
Note 2:
Note 3:
T
T
T
T
ARB
ARB
ARB
opr
t10
t11
t12
t13
t1
t2
t3
t4
t5
t6
t7
t8
t9
is the period of operation clock. It depends on CKUP1 and CKUP0 bits
is the Arbitration Clock Period
is identical to T
is twice T
Figure 14 - Multiplexed Bus, 80xx-Like Control Signals; Write Cycle
Address Setup to ALE Low
Address Hold from ALE Low
nCS Setup to ALE Low
nCS Hold from ALE Low
ALE Low to nDS Low
Valid Data Setup to nDS High
Data Hold from nDS High
ALE High Width
ALE Low Width
nWR Low Width
nWR High Width
nRD
Cycle Time (nWR
Write cycle for Address Pointer Low Register occurring after a read from Data
Register requires a minimum of 5T
leading edge of nWR.
Write cycle for Address Pointer Low Register occurring after a write to Data
Register requires a minimum of 5T
leading edge of the next nWR.
Any cycle occurring after a write to Address Pointer Low Register requires a
minimum of 4T
next nWR.
The Microcontroller typically accesses the COM20020 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20020 cycles.
opr
if SLOW ARB = 1
t9
to nWR Low
t1
opr
VALID
t3
if SLOW ARB = 0
t13
ARB
Parameter
Note 3
from the trailing edge of nWR to the leading edge of the
t2,
t4
to Next
t5
DATASHEET
)**
ARB
ARB
Page 51
from the trailing edge of nWR to the
from the trailing edge of nRD to the
t10
t11
VALID DATA
t6
4T
min
20
20
20
20
20
30
10
20
10
10
10
15
ARB
*
max
t7
Note 2
units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
t12
t8**
t8
Revision 09-11-06