COM20020I-HD SMSC, COM20020I-HD Datasheet - Page 25

• Manufacturer Part Number: COM20020I-HD
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20020I-HD

• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Supply Current (max): 40 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADDR
Note*: (R/W) These bits can be Written or Read. For more information see Appendix C.
6.2
The COM20020I 3V contains 14 internal registers. Table 2 and Table 3 illustrate the COM20020I 3V register map. All
undefined bits are read as undefined and must be written as logic "0".
Interrupt Mask Register (IMR)
The COM20020I 3V is capable of generating an interrupt signal when certain status bits become true. A write to the IMR
specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR are in the same position
as their corresponding status bits in the Status Register and Diagnostic Status Register. A logic "1" in a particular position
enables the corresponding interrupt. The Status bits capable of generating an interrupt include the Receiver Inhibited bit,
New Next ID bit, Excessive NAK bit, Reconfiguration Timer bit, and Transmitter Available bit. No other Status or
Diagnostic Status bits can generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to produce the interrupt
signal. An RI or TA interrupt is masked when the corresponding mask bit is reset to logic "0", but will reappear when the
corresponding mask bit is set to logic "1" again, unless the interrupt status condition has been cleared by this time. A
RECON interrupt is cleared when the "Clear Flags" command is issued. An EXCNAK interrupt is cleared when the
"POR Clear Flags" command is issued. A New Next ID interrupt is cleared by reading the Next ID Register. The
Interrupt Mask Register defaults to the value 0000 0000 upon hardware reset.
Data Register
This read/write 8-bit register is used as the channel through which the data to and from the RAM passes. The data is
placed in or retrieved from the address location presently specified by the address pointer. The contents of the Data
Register are undefined upon hardware reset. In case of READ operation, the Data Register is loaded with the contents
of COM20020I 3V Internal Memory upon writing Address Pointer low only once.
Tentative ID Register
The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up accordingly
(please refer to the Configuration Register and SUB ADR Register). The Tentative ID Register can be used while the
node is on-line to build a network map of those nodes existing on the network. It minimizes the need for operator
SMSC COM20020I 3.3V Rev.E
07-0
07-1
07-2
07-3
07-4
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
00
01
02
03
04
05
06
RI/TR1
P1-MO
RD-DA
RBUS-
(R/W)*
RESE
NID7
MSB
TID7
TMG
INTERNAL REGISTERS
DE
C7
TA
A7
D7
T
0
CCHEN
AUTO-
(R/W)*
FOUR
NAKS
NID6
TID6
INC
C6
A6
D6
0
0
0
TXEN
NID5
TID5
C5
A5
D5
0
0
0
0
0
0
Table 3 - Write Register Summary
CKUP
NID4
RCV-
TID4
ET1
ALL
C4
D4
A4
0
0
0
0
WRITE
DATASHEET
EXCNAK
CKP3
NID3
TID3
ET2
C3
A3
D3
EF
Page 25
0
0
0
PLANE
SUB-A
BACK-
RECO
SYNC
CKP2
TID2
NID2
A10
NO-
C2
D2
D2
A2
N
0
NEXTID
CKP1
SUB-
SUB-
RCN-
NEW
NID1
TID1
TM1
AD1
AD1
C1
A9
A1
D1
0
SLOW-
RCN-
SUB-
SUB-
NID0
TID0
LSB
ARB
TM0
AD0
AD0
TTA
TA/
C0
A8
A0
D0
0
INTERRUPT
COMMAND
REGISTER
ADDRESS
ADDRESS
PTR HIGH
PTR LOW
URATION
SUBADR
CONFIG-
NODEID
SETUP1
SETUP2
TENTID
MASK
DATA
TEST
Revision 09-11-06