COM20020I3V-HT SMSC, COM20020I3V-HT Datasheet - Page 36

• Manufacturer Part Number: COM20020I3V-HT
• Description: Network Controller & Processor ICs ARCNET Contrllr
• Manufacturer: SMSC

Specifications of COM20020I3V-HT

• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 35 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Sequential Access Memory
The internal RAM is accessed via a pointer-based scheme. Rather than interfering with system memory, the internal
RAM is indirectly accessed through the Address High and Low Pointer Registers. The data is channeled to and from the
microcontroller via the 8-bit data register. For example: a packet in the internal RAM buffer is read by the microcontroller
by writing the corresponding address into the Address Pointer High and Low Registers (offsets 02H and 03H). Note that
the High Register should be written first, followed by the Low Register, because writing to the Low Register loads the
address. At this point the device accesses that location and places the corresponding data into the data register. The
microcontroller then reads the data register (offset 04H) to obtain the data at the specified location. If the Auto Increment
bit is set to logic "1", the device will automatically increment the address and place the next byte of data into the data
register, again to be read by the microcontroller. This process is continued until the entire packet is read out of RAM.
Refer to Figure 8 for an illustration of the Sequential Access operation. When switching between reads and writes, the
pointer must first be written with the starting address. At least one cycle time should separate the pointer being loaded
and the first read (see timing parameters).
Access Speed
The COM20020I 3V is able to accommodate very fast access cycles to its registers and buffers. Arbitration to the buffer
does not slow down the cycle because the pointer based access method allows data to be prefetched from memory and
stored in a temporary register. Likewise, data to be written is stored in the temporary register and then written to memory.
For systems which do not require quick access time, the arbitration clock may be slowed down by setting bit 0 of the
Setup1 Register equal to logic "1". Since the Slow Arbitration feature divides the input clock by two, the duty cycle of the
input clock may be relaxed.
SOFTWARE INTERFACE
The microcontroller interfaces to the COM20020I 3V via software by accessing the various registers. These actions are
described in the Internal Registers section. The software flow for accessing the data buffer is based on the Sequential
Access scheme. The basic sequence is as follows:
The software flow for controlling the Configuration, Node ID, Tentative ID, and Next ID registers is generally limited to the
initialization sequence and the maintenance of the network map.
Additionally, it is necessary to understand the details of how the other Internal Registers are used in the transmit and
receive sequences and to know how the internal RAM buffer is properly set up. The sequence of events that tie these
actions together is discussed as follows.
Selecting RAM Page Size
During normal operation, the 2K x 8 of RAM is divided into four pages of 512 bytes each. The page to be used is specified
in the "Enable Transmit (Receive) from (to) Page fnn" command, where "nn" specifies page 0, 1, 2, or 3.
This allows the user to have constant control over the allocation of RAM.
When the Offset bit "f" (bit 5 of the "Enable Transmit (Receive) from (to) Page fnn" command word) is set to logic "1", an
offset of 256 bytes is added to the page specified. For example: to transmit from the second half of page 0, the command
"Enable Transmit from Page fnn" (fnn=100 in this case) is issued by writing 0010 0011 to the Command Register. This
allows a finer resolution of the buffer pages without affecting software compatibility. This scheme is useful for applications
which frequently use packet sizes of 256 bytes or less, especially for microcontroller systems with limited memory
capacity. The remaining portions of the buffer pages which are not allocated for current transmit or receive packets may
be used as temporary storage for previous network data, packets to be sent later, or as extra memory for the system,
which may be indirectly accessed.
If the device is configured to handle both long and short packets (see "Define Configuration" command), then receive
pages should always be 512 bytes long because the user never knows what the length of the receive packet will be. In
this case, the transmit pages may be made 256 bytes long, leaving at least 512 bytes free at any given time. Even if the
Command Chaining operation is being used, 512 bytes is still guaranteed to be free because Command Chaining only
SMSC COM20020I 3.3V Rev.E
5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Disable Interrupts
Write to Pointer Register High (specifying Auto-Increment mode)
Write to Pointer Register Low (this loads the address)
Enable Interrupts
Read or Write the Data Register (repeat as many times as necessary to empty or fill the buffer)
The pointer may now be read to determine how many transfers were completed.
DATASHEET
Page 36
Revision 09-11-06