LAN91C96TQFP SMSC, LAN91C96TQFP Datasheet - Page 52

• Manufacturer Part Number: LAN91C96TQFP
• Description: Ethernet ICs Non-PCI 10 Mbps Ethernet MAC
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN91C96TQFP

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 5 V
• Supply Voltage (min): 0 V
• Supply Current (max): 95 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note:
Revision 1.0 (10-24-08)
ENABLE
I/O SPACE - BANK1
This register can be used as a way of storing and retrieving non-volatile information in the EEPROM to be
used by the software driver. The storage is word oriented, and the EEPROM word address to be read or
written is specified using the six lowest bits of the Pointer Register.
This register can also be used to sequentially program the Individual Address area of the EEPROM, that is
normally protected from accidental Store operations.
This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control
Register is set. This allows generic EEPROM read and write routines that do not affect the basic setup of
the LAN91C96.
I/O SPACE - BANK1
RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate
interrupts and their memory is released.
PWRDN - Active high bit used to put the Ethernet function in power down mode.
Cleared by:
1.
2.
WAKUP_EN - Active high bit used to enable the controller in the appropriate power down modes to power
up and set the WAKEUP bit in the EPHSR -> generate an EPH interrupt(if not masked). When clear (0),
no “Magic Packet” scanning is done on receive packets.
Setting (1) the bit is meaningful only if the function is enabled (Enable Function bit in COR; offset 8000h).
OFFSET
OFFSET
LE
0
0
0
A write to any register in the LAN91C96 I/O space.
Hardware reset. This bit is combined with the Pwrdwn bit in ECSR and with the powerdown bit to
determine when the function is powered down.
A
C
0
0
ENABLE
RCV_
BAD
CR
0
0
0
0
GENERAL ADDRESS REGISTERS
ENABLE
PWRDN
TE
CONTROL REGISTER
0
0
0
0
DATASHEET
NAME
NAME
WAKEUP
HIGH DATA BYTE
LOW DATA BYTE
_EN
X
0
0
0
Page 52
RELEAS
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
AUTO
0
0
E
X
0
READ/WRITE
READ/WRITE
EEPROM
SELECT
0
0
TYPE
TYPE
X
0
0
0
RELOAD
X
0
SYMBOL
SYMBOL
SMSC LAN91C96 5v&3v
GPR
0
0
CTR
STORE
1
1
0
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