MT88E39ASR1 Zarlink, MT88E39ASR1 Datasheet
MT88E39ASR1
Specifications of MT88E39ASR1
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MT88E39ASR1 Summary of contents
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... Copyright 1998 - 2004, Zarlink Semiconductor Inc. All Rights Reserved. Calling Number Identification Circuit MT88E39AS MT88E39ASR MT88E39AS1 MT88E39ASR1 Description The MT88E39 Calling Number Identification Circuit (CNIC1. CMOS integrated circuit which provides an interface to calling line information delivery services that utilize 1200 baud Bell 202 or CCITT V.23 FSK data transmission schemes ...
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... DATA bit. MT88E39 1 16 IN+ VDD 2 15 IN- IC MODE* 13 VRef 4 PWDN 5 12 CAP CD 11 OSC1 OSC2 7 DATA 9 VSS 8 DCLK 16 PIN SOIC Figure 2 - Pin Connections Description . This is used to bias the op-amp inputs Zarlink Semiconductor Inc. Data Sheet * Was IC1 in MT88E41 ** Was IC2 in MT88E41 ...
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... CPE, the FSK accept level will become lower as the batteries are run down. If the CPE is designed for 4.5 V, the accept level will be lowered when the batteries drain North America there is a requirement for rejecting FSK signals which are below 3 mVrms when data is not preceded by ringing, such as VMWI (Visual MT88E39 Description 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Note that in mode 0 DR and CD are open drain outputs; in mode 1 they are CMOS outputs. DCLK is an output in mode 0, an input in mode 1. MT88E39 R1 IN Ref MT88E39 INPUT IMPEDANCE (Z diff Figure 3 - Differential Input Configuration IN+ IN VOLTAGE GAIN Ref ( MT88E39 Figure 4 - Single-Ended Input Configuration 4 Zarlink Semiconductor Inc. Data Sheet Ref (1/ωC) ) which is ...
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... Note that signals such as CAS, speech and DTMF tones also lie in the FSK frequency band and the carrier detector may be activated by these signals. They will be demodulated and presented as data. To avoid false data, the PWDN pin should be used to disable the FSK demodulator when no FSK signal is expected. MT88E39 5 Zarlink Semiconductor Inc. Data Sheet ...
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... GS when the single tone noise is added. MT88E39 MT88E39 MT88E39 OSC1 OSC2 OSC1 OSC2 next MT88E39 (For 5 V application only) Figure 5 - Common Crystal Connection and is used to bias the input op-amp. A 0.1 µ suppress noise Ref. 6 Zarlink Semiconductor Inc. Data Sheet to the ...
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... Vdd 200 K 5% (Ring Detect) Motorola 4N25 10 nF 464 K 5% For ETSI applications, set input gain = -2.5 dB: For ETSI applications, set input gain = -5.5 dB: Figure 6 - Application Circuit 7 Zarlink Semiconductor Inc. Data Sheet Vdd 100 nF 20% MT88E39 V IN+ DD Vdd Vdd IC IN- 1 ...
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... Vdd Vdd can be opened and D1 shorted if the microcontroller does not read the INT1 pin. Vdd R2 * *R2 can be omitted if mode 1 is selected 8 Zarlink Semiconductor Inc. Data Sheet *1 *2 Europe: ETSI 1300 Hz +/- 1.5% 2100 Hz +/- 1.5% *3 -33.78 to -5.78 dBm * dBV ) -47.78 dBm (-50 dBV) ...
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... 0.48 0.28 0.2 HYS V 0.7 0.5*V - 0.1 Ref DD R Ref 9 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.3 6 -0.3 V +0.3 DD ±10 mA -65 +150 500 mW ) unless otherwise stated. SS Max. Units Test Conditions 5.5 V MHz ±0.2 % °C +85 Test Max. Units Conditions µA ...
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... SNR Zarlink Semiconductor Inc. Data Sheet Units Test Conditions µA ≤ V ≤ MΩ kHz ripple ≤ V ≤ CMmin IN CMmax dB MHz Load ≥ 100 kΩ ...
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... CDD 1200.4 1202.8 1205.2 t 415 416 417 CH t 415 416 417 CL t 415 416 417 CRD 200 FF t 415 416 417 RL 11 Zarlink Semiconductor Inc. Data Sheet Units Notes* ms µ Units. Notes* bps µ µ µs 2 µs 2 µs 2 µs ...
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... Figure 8 - DATA and DCLK Output Timing (Mode 0) MT88E39 ‡ Sym. Min. Typ. f DCLK1 30 t 500 DDS t 500 DDH t t DCD CDD Figure Output Timing (Mode 0) 12 Zarlink Semiconductor Inc. Data Sheet Max. Units Notes* 1 MHz See Fig 100 ns ns See Fig See Fig ...
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... Figure 11 - Serial Data Interface Timing (Mode 0) MT88E39 checksum channel seizure Mark state Input FSK 500 ms Data (min) t IAL start stop start stop t CRD 13 Zarlink Semiconductor Inc. Data Sheet Second Ring 200 ms (min IAH High (Input Idle) start stop start stop ...
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... The DCLK input must be low before and after DR falling edge DCLK clears DR ¿ ¡ DCLK does not clear DR low for maximum time (1/2 bit time) Figure 12 - Serial Data Interface Timing (Mode 1) MT88E39 word N DCLK1 Zarlink Semiconductor Inc. Data Sheet stop ¡ 0 ...
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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...