MT88E39ASR1 Zarlink, MT88E39ASR1 Datasheet - Page 4

• Manufacturer Part Number: MT88E39ASR1
• Description: Caller ID CMOS 3.58MHz 3.3V/5V 16-Pin SOIC T/R
• Manufacturer: Zarlink

Specifications of MT88E39ASR1

• Package: 16SOIC
• Telecommunication Standards Supported: ETSI 300 778-1|GR-30|SR-TSV-002476|TIA/EIA-716
• Fabrication Technology: CMOS
• Maximum Data Rate: 1212 Bd
• Typical Operating Supply Voltage: 3.3|5 V
• Typical Supply Current: 1.9 mA
• Minimum Operating Temperature: -40 °C
• Maximum Operating Temperature: 85 °C
• Operating Frequency: 3.58 MHz

Message Waiting Indicator) applications. When the batteries are drained, the CPE will not meet the reject level. For
on-hook Caller ID, there is no reject level and the CPE will meet all requirements.
Input Configuration
The input arrangement of the MT88E39 provides an operational amplifier, as well as a bias source (V
used to bias the inputs at V
for adjustment of gain.
Figure 3 shows the necessary connections for a differential input configuration. In a single-ended configuration, the
input pins are connected as shown in Figure 4.
3-wire FSK Data Interface
The MT88E39 provides a powerful dual mode 3-wire interface so that the 8-bit data words in the demodulated FSK
bit stream can be extracted without the need either for an external UART or for the microcontroller to perform the
UART function in software. The interface is specifically designed for the 1200 baud rate and is comprised of the
DATA, DCLK (data clock) and DR (data ready) pins. Two modes (0 and 1) are selectable via control of the device’s
MODE pin. In mode 0 the FSK bit stream is output as demodulated. In mode 1 the FSK data byte is store in a 1 byte
buffer. Note that in mode 0 DR and CD are open drain outputs; in mode 1 they are CMOS outputs. DCLK is an
output in mode 0, an input in mode 1.
DD
/2
. Provision is made for connection of a feedback resistor to the op-amp output (GS)
DIFFERENTIAL INPUT AMPLIFIER
VOLTAGE GAIN
(A
C1 = C2
R1 = R4
R3 = (R2 x R5) / (R2 + R5)
For unity gain, R5 = R1
V
diff) = R5/R1
Figure 4 - Single-Ended Input Configuration
VOLTAGE GAIN
(A
Figure 3 - Differential Input Configuration
V
C
) = R
C2
C1
F
/ R
R
R1
R4
IN
IN
Zarlink Semiconductor Inc.
R3
MT88E39
4
INPUT IMPEDANCE
(Z
R2
R
R5
IN
F
diff) = 2
IN+
IN-
GS
V
V
GS
IN+
IN-
Ref
Ref
MT88E39
MT88E39
R1
2
+ (1/ωC)
2
Data Sheet
Ref
) which is