AD7538JRZ Analog Devices Inc, AD7538JRZ Datasheet - Page 12

• Manufacturer Part Number: AD7538JRZ
• Description: DAC 1-CH R-2R 14-Bit 24-Pin SOIC W
• Manufacturer: Analog Devices Inc

Specifications of AD7538JRZ

• Package: 24SOIC W
• Resolution: 14 Bit
• Conversion Rate: 667 KSPS
• Architecture: R-2R
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 1
• Output Type: Current
• Full Scale Error: ±8 LSB
• Integral Nonlinearity Error: ±2 LSB
• Maximum Settling Time: 1.5 us
• Settling Time: 1.5µs
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 1W
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Number Of Channels: 1
• Interface Type: Parallel
• Single Supply Voltage (typ): 12/15V
• Dual Supply Voltage (typ): Not RequiredV
• Power Supply Requirement: Single
• Single Supply Voltage (min): 11.4V
• Single Supply Voltage (max): 15.75V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 24
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7538
PROGRAMMABLE GAIN AMPLIFIER
The circuit shown in Figure 9 provides a programmable gain
amplifier (PGA). In it the DAC behaves as a programmable
resistance and thus allows the circuit gain to be digitally
controlled.
The transfer function of Figure 9 is:
R
V
where:
n is the resolution of the DAC.
N is the DAC input code in decimal.
R
EQ
IN
REF
is the constant input impedance of the DAC (R
is the equivalent transfer impedance of the DAC from the
pin to the I
Gain
R
EQ
NOTES
1. RESISTOR R
V
IN
=
INCLUDED ON THE DICE.
=
2
V
Figure 9. Programmable Gain Amplifier (PGA)
V
n
OUT
N
R
R
IN
FB
OUT
IN
=
pin and can be expressed as
FB
−
IS ACTUALLY
R
R
A
EQ
FB
A
I
GND
OUT
V
DIGITAL
V
INPUT
AD7538
DD
SS
N
V
V
REF
DD
V
IN
OUT
= R
LAD
).
Rev. B | Page 12 of 16
(1)
(2)
Substituting this expression into Equation 1 and assuming
zero gain error for the DAC (R
simplifies to
The ratio N/2
such, is the fractional representation of the digital input word.
Equation 4 indicates that the gain of the circuit can be varied
from 16,384 down to unity (actually 16,384/16,383) in 16,383
steps. The all 0s code is never applied. This avoids an open-loop
condition thereby saturating the amplifier. With the all 0s code
excluded there remains (2
choice of (2
20
V
V
V
V
OUT
OUT
IN
IN
log
10
=
=
n
– 1) output levels. In decibels the dynamic range is
−
−
n
V
V
is commonly represented by the term, D, and, as
OUT
2
−
N
IN
N
n
2
n
=
=
20
−
D
1
log
n
– 1) possible input codes allowing a
10
(
2
IN
n
= R
−
1
)
FB
=
), the transfer function
84
dB
(3)
(4)