ADSP-21061LKBZ-160 Analog Devices Inc, ADSP-21061LKBZ-160 Datasheet - Page 22

• Manufacturer Part Number: ADSP-21061LKBZ-160
• Description: DSP Floating-Point 32-Bit 40MHz 40MIPS 225-Pin BGA
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061LKBZ-160

• Package: 225BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 40 MHz
• Ram Size: 128 KB
• Device Million Instructions Per Second: 40 MIPS
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21061/ADSP-21061L
Clock Input
Table 7. Clock Input
Reset
Table 8. Reset
1
2
Parameter
Timing Requirements
t
t
t
t
Parameter
Timing Requirements
t
t
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable
Only required if multiple ADSP-21061s must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21061s commu-
CK
CKL
CKH
CKRF
WRST
SRST
V
nicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
DD
and CLKIN (not including startup time of external clock oscillator).
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
RESET Pulse Width Low
RESET Setup Before CLKIN High
RESET
CLKIN
CLKIN
1
2
Min
20
7
5
ADSP-21061
50 MHz, 5 V
Rev. C | Page 22 of 56 | July 2007
Figure 9. Clock Input
t
Max
100
3
Figure 10. Reset
CKH
Min
22.5
7
5
t
WRST
ADSP-21061L
44 MHz, 3.3 V
t
t
CK
CKL
Min
4t
14 + DT/2
CK
Max
100
3
Min
25
7
5
ADSP-21061L
ADSP-21061/
5 V and 3.3 V
t
SRST
5 V and 3.3 V
40 MHz,
Max
100
3
Max
t
CK
Min
30
7
5
ADSP-21061
33 MHz, 5 V
Max
100
3
Unit
ns
ns
Unit
ns
ns
ns
ns