ADSP-21061LKBZ-160 Analog Devices Inc, ADSP-21061LKBZ-160 Datasheet - Page 29

• Manufacturer Part Number: ADSP-21061LKBZ-160
• Description: DSP Floating-Point 32-Bit 40MHz 40MIPS 225-Pin BGA
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21061LKBZ-160

• Package: 225BGA
• Numeric And Arithmetic Format: Floating-Point
• Maximum Speed: 40 MHz
• Ram Size: 128 KB
• Device Million Instructions Per Second: 40 MIPS
• Interface: Synchronous Serial Port (SSP)
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 128kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 225-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21061 bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave)
timing requirements.
Table 15. Synchronous Read/Write—Bus Slave
1
2
3
4
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
This specification applies to the ADSP-21061LKS-176 (3.3 V, 44 MHz) and the ADSP-21061KS-200 (5 V, 50 MHz), operating at t
See
t
SRWLI
DACKAD
SADRI
HADRI
SRWLI
HRWLI
RWHPI
SDATWH
HDATWH
SDDATO
DATTR
DACKAD
ACKTR
preceding timing specification of the same name.
times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of
the state of MMSWS or strobes. A slave will three-state ACK every cycle with t
Example System Hold Time Calculation on Page 44
(min) = 9.5 + 5DT/16 when multiprocessor memory space wait state (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t
is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and inputs have setup
Address, SW Setup Before CLKIN
Address, SW Hold After CLKIN
RD/WR Low Setup Before CLKIN
RD/WR Low Hold After CLKIN
44 MHz/50 MHz
RD/WR Pulse High
Data Setup Before WR High
Data Hold After WR High
Data Delay After CLKIN
Data Disable After CLKIN
ACK Delay After Address, SW
ACK Disable After CLKIN
2
for calculation of hold times given capacitive and dc loads.
2
3
4
Rev. C | Page 29 of 56 | July 2007
1
ACKTR
.
Min
14 + DT/2
8.5 + 5DT/16
–4 – 5DT/16
–3.5 – 5DT/16
3
3
1
0 – DT/8
–1 – DT/8
ADSP-21061/ADSP-21061L
5 V and 3.3 V
CK
< 25 ns. For all other devices, use the
Max
5 + DT/2
8 + 7DT/16
8 + 7DT/16
19 + 5DT/16
7 – DT/8
8
6 – DT/8
SRWLI
(min)= 4 + DT/8.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns