SI5326C-C-GM Silicon Laboratories Inc, SI5326C-C-GM Datasheet - Page 20

• Manufacturer Part Number: SI5326C-C-GM
• Description: DSPLL 36-Pin QFN EP
• Manufacturer: Silicon Laboratories Inc
• Type: Jitter Attenuatorr

Specifications of SI5326C-C-GM

• Package: 36QFN EP
• Operating Temperature: -40 to 85 °C
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 346MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Frequency-max: 346MHz
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: QFN EP
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1746; 336-1746-5; 336-1746

Register
10
11
16
17
18
19
20
21
22
23
24
25
31
32
0
1
2
3
4
5
6
7
8
9
Si5326
5. Register Map
All register bits that are not defined in this map should always be written with the specified Reset Values. The
writing to these bits of values other than the specified Reset Values may result in undefined device behavior.
Registers not listed, such as Register 64, should never be written to.
20
FLAT_VALID
INCDEC_
FOS_EN
AUTOSEL_REG[1:0]
PIN
CKSEL_REG[1:0]
D7
HLOG_2[1:0]
ICMOS[1:0]
FREE_RUN
N1_HS[2:0]
SLEEP
BWSEL_REG[3:0]
D6
FOS_THR[1:0]
HIST_AVG[4:0]
ALWAYS_
CKOUT_
DHOLD
ON
D5
HLOG_1[1:0]
SFOUT2_REG[2:0]
SQ_ICAL
Rev. 1.0
D4
NC1_LS[15:8]
VALTIME[1:0]
CLAT[7:0]
FLAT[7:0]
CK_ACTV_
FLAT[14:8]
DSBL2_
BAD_
CK2_
REG
POL
PIN
D3
CK_PRIOR2[1:0]
HST_DEL[4:0]
LOS2_MSK
FOS2_MSK
CK_BAD_
DSBL1_
BAD_
CK1_
REG
POL
PIN
D2
NC1_LS[19:16]
SFOUT1_REG[2:0]
FOSREFSEL[2:0]
CK1_ACTV_
LOCK[T2:0]
LOS1_MSK
FOS1_MSK
BYPASS_
LOL_POL
LOL_PIN
PD_CK2
REG
PIN
D1
CK_PRIOR[1:0]
CKSEL_PIN
LOSX_MSK
LOL_MSK
INT_POL
PD_CK1
INT_PIN
D0