SI5326C-C-GM Silicon Laboratories Inc, SI5326C-C-GM Datasheet - Page 28

• Manufacturer Part Number: SI5326C-C-GM
• Description: DSPLL 36-Pin QFN EP
• Manufacturer: Silicon Laboratories Inc
• Type: Jitter Attenuatorr

Specifications of SI5326C-C-GM

• Package: 36QFN EP
• Operating Temperature: -40 to 85 °C
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 346MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.71 V ~ 3.63 V
• Mounting Type: Surface Mount
• Package / Case: 36-QFN
• Frequency-max: 346MHz
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: QFN EP
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 336-1746; 336-1746-5; 336-1746

Si5326
Reset value = 0000 0000
Reset value = 1100 0000
28
Register 8.
Register 9.
Name
Name
Type
Type
7:6
5:4
3:0
7:3
2:0
Bit
Bit
Bit
Bit
HLOG_2 [1:0] HLOG_2 [1:0].
HIST_AVG
Reserved
Reserved
Name
Name
D7
D7
[4:0]
HLOG_2[1:0]
R/W
00: Normal operation
01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT2 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
HLOG_1 [1:0].
00: Normal operation
01: Holds CKOUT1 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT1 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
Reserved.
HIST_AVG [4:0].
Selects amount of averaging time to be used in generating the history information for
Digital Hold.
See the Si53xx Family Reference Manual for a detailed description
Reserved.
D6
D6
HIST_AVG [4:0]
R/W
D5
D5
HLOG_1[1:0]
R/W
Rev. 1.0
D4
D4
Function
Function
D3
D3
D2
D2
R
Reserved
R
Reserved
D1
D1
R
D0
D0
R