M25P20-VMN6PB NUMONYX, M25P20-VMN6PB Datasheet

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M25P20-VMN6PB

Manufacturer Part Number
M25P20-VMN6PB
Description
Flash Mem Serial-SPI 3.3V 2M-Bit 256K x 8 8ns 8-Pin SO N Tray
Manufacturer
NUMONYX
Datasheet

Specifications of M25P20-VMN6PB

Package
8SO N
Cell Type
NOR
Density
2 Mb
Architecture
Sectored
Block Organization
Symmetrical
Typical Operating Supply Voltage
3.3 V
Sector Size
64KByte x 4
Timing Type
Synchronous
Operating Temperature
-40 to 85 °C
Interface Type
Serial-SPI

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Feature summary
March 2010
– JEDEC Standard two-Byte Signature
– Unique ID code (UID) with 16 bytes read-
– RES Instruction, One-Byte, Signature
– ECOPACK® (RoHS compliant)
2 Mbit of Flash Memory
Page Program (up to 256 Bytes) in 0.8 ms
(typical)
Sector Erase (512 Kbit) in 0.6 s (typical)
Bulk Erase (2 Mbit) in 3 s (typical)
2.3 to 3.6 V Single Supply Voltage
SPI Bus Compatible Serial Interface
75 MHz Clock Rate (maximum)
Deep Power-down Mode 1 μA (typical)
Hardware Write Protection: protected area
size defined by two non-volatile bits (BP0,
BP1)
Electronic Signatures
Packages
(2012h)
only, available upon customer request
(11h), for backward compatibility
2 Mbit, low voltage, Serial Flash memory
Rev 14
with 75 MHz SPI bus interface
(MLP8 6 x 5 mm)
VFQFPN8 (MP)
MLP8 6 x 5 mm
150 mils width
QFN8L (MS)
SO8 (MN)
M25P20
www.Numonyx.com
1/55
1

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M25P20-VMN6PB Summary of contents

Page 1

... RES Instruction, One-Byte, Signature (11h), for backward compatibility Packages – ECOPACK® (RoHS compliant) March 2010 2 Mbit, low voltage, Serial Flash memory with 75 MHz SPI bus interface Rev 14 M25P20 SO8 (MN) 150 mils width QFN8L (MS) MLP8 VFQFPN8 (MP) (MLP8 mm) 1/55 www.Numonyx.com ...

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Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

Read Data Bytes (READ ...

Page 4

List of tables Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of figures Figure 1. Logic Diagram ...

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... Summary description The M25P20 Mbit (256K x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25P20 features high performance instructions allowing clock frequency operation MHz The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction ...

Page 7

... PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1. Table 1. Signal Names C Serial Clock D Serial Data Input Q Serial Data Output S Chip Select W Write Protect HOLD Hold V Supply Voltage CC V Ground SS M25P20 HOLD AI04081B , SS 7/55 ...

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Signal description 2.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). 2.2 Serial Data Input (D) This input ...

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SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge ...

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Figure 4. SPI modes supported CPOL CPHA 10/55 MSB MSB AI01438B ...

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Operating features 4.1 Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the ...

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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P20 features the following data protection mechanisms: Power On Reset and an internal timer (t inadvertant changes while the power supply is outside the operating specification. ...

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Table 2. Protected Area Sizes Status Register Content BP1 Bit BP0 Bit The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) ...

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Figure 5. Hold Condition Activation C HOLD 14/55 Hold Condition (standard use) (non-standard use) Hold Condition AI02029D ...

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Memory organization The memory is organized as: 262,144 bytes (8 bits each) 4 sectors (512 Kbits, 65536 bytes each) 1024 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device ...

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Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven ...

Page 17

Table 4. Instruction Set Instruction WREN Write Enable WRDI Write Disable (1) RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes Read Data Bytes at Higher FAST_READ Speed PP Page Program SE Sector Erase ...

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Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is ...

Page 19

... Device identification (2 bytes) A Unique ID code (UID) (17 bytes, of which 16 available upon customer request). The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (12h). ...

Page 20

Figure 9. Read Identification (RDID) Instruction Sequence and Data-Out Sequence High Impedance Q 6.4 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may ...

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BP1, BP0 bits The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When ...

Page 22

Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable ...

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Table 7. Protection Modes W SRWD Write Protection of the Mode Signal Bit Status Register 1 0 Status Register is Writable (if the WREN instruction 0 0 Software has set the WEL bit) Protected The values in the SRWD, (SPM) ...

Page 24

Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising ...

Page 25

Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) ...

Page 26

Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the ...

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Figure 14. Page Program (PP) Instruction Sequence Instruction Data Byte ...

Page 28

Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...

Page 29

Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...

Page 30

Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the ...

Page 31

... Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic Signature, whose value for the M25P20 is 11h. Except while an Erase, Program or Write Status Register cycle is in progress, the Release ...

Page 32

... C Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P20, is 11h. Figure 19. Release from Deep Power-down (RES) Instruction Sequence Instruction D High Impedance Q Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time ...

Page 33

Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay ...

Page 34

Figure 20. Power-up Timing (max (min) Reset State of the Device V WI Table 8. Power-Up Timing and V Symbol ( (min low VSL CC (1) t Time delay to ...

Page 35

... V Electrostatic Discharge voltage (Human Body model) ESD 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. The minimum voltage may reach the value for no more than 20 ns during transitions; The maximum voltage may reach the value JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω ...

Page 36

DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...

Page 37

Table 13. DC Characteristics (Device Grade 6) Symbol Parameter I Input Leakage Current LI Output Leakage I LO Current I Grade 6 CC1, Standby Current I Grade 3 CC1, I Grade 6 Deep Power-down CC2, Current I Grade 3 CC2, ...

Page 38

Table 14. DC Characteristics (Device Grade 3) Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Deep Power-down Current CC2 I Operating Current (READ) CC3 I Operating Current (PP) CC4 I Operating ...

Page 39

Table 17. Instruction Times (Device Grade 3) Test conditions specified in Symbol Alt. t Write Status Register Cycle Time W Page Program Cycle Time (256 Bytes) ( Page Program Cycle Time (n Bytes) t Sector Erase Cycle Time ...

Page 40

Table 19. AC Characteristics (25MHz Operation, Device Grade Symbol Alt ( CLH ( CLL (2) t CLCH (2) t CHCL t t SLCH CSS t ...

Page 41

Table 20. AC Characteristics (40MHz Operation, Device Grade 6) 40MHz available for products marked since week 20 of 2004, only Test conditions specified in Symbol Alt. Clock Frequency for the following f f instructions: FAST_READ, PP, SE, BE ...

Page 42

It is 30µs in devices produced with the “X” process technology. Details of how to find the process letter on the device marking are given in the Application note AN1995. Table 21. AC Characteristics (50MHz Operation, Device Grade 6) ...

Page 43

Value guaranteed by characterization, not 100% tested in production. 5. Expressed as a slew-rate. 6. Only applicable as a constraint for a WRSR instruction ...

Page 44

Table 22. AC characteristics, grade 2.7 V (continued) Applies only to products made with T9HX technology, identified with process digit ‘4’ Symbol Alt. S High to Standby mode without Read Elec- (5) t RES1 tronic Signature S ...

Page 45

Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL High Impedance Q Figure 24. Hold Timing HOLD tHLCH tCHHL tCHHH tHLQZ tHHQX tSHWL AI07439 tHHCH AI02032 45/55 ...

Page 46

Figure 25. Output Timing S C tCLQV tCLQX tCLQX Q ADDR. D LSB IN 46/55 tCH tCLQV tCL tQLQH tQHQL tSHQZ LSB OUT AI01449e ...

Page 47

Package mechanical Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline Drawing is not to scale. 2. The ‘1’ that appears in the top view of the package shows ...

Page 48

Figure 27. QFN8L (MLP8) 8-lead, dual flat package no lead, 6 × 5 mm, package outline Drawing is not to scale. Table 24. QFN8L (MLP8) 8-lead dual flat package no lead ...

Page 49

Figure 28. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Dual Flat Package No lead, 6x5mm, Package Outline Drawing is not to scale. 2. The circle in the top view of the package indicates ...

Page 50

... Numonyx Sales Office. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 50/55 M25P20 – V (4) . ...

Page 51

... Tested Parts from the non Auto Tested parts). Note: Numonyx strongly recommends the use of the Automotive Grade devices (Auto Grade 6 and automotive envirnoment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your Numonyx sales office for a copy. M25P20 – ...

Page 52

Revision history Table 28. Document revision history Date Revision 12-Apr-2001 1.0 25-May-2001 1.1 11-Sep-2001 1.2 16-Jan-2002 1.3 16-May-2002 1.4 12-Sep-2002 1.5 13-Dec-2002 1.6 24-Nov-2003 2.0 26-Apr-2004 3.0 05-Aug-2004 4.0 21-Dec-2004 5.0 01-Aug-2005 6.0 52/55 Changes Document written Serial Paged ...

Page 53

... SO8 Narrow package specifications updated (see Table 23). 10-Dec-2008 11 Applied Numonyx branding. Changed frequency up to 75MHz (only in the standard Vcc range). Added new package. 12-Oct-2008 12 Added UID/CFD protection. Extended Vcc range to 2.3 V. Created separate order information for standard parts and automotive ...

Page 54

... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...

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