M25P20-VMN6TPB NUMONYX, M25P20-VMN6TPB Datasheet
M25P20-VMN6TPB
Specifications of M25P20-VMN6TPB
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M25P20-VMN6TPB Summary of contents
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... RES Instruction, One-Byte, Signature (11h), for backward compatibility Packages – ECOPACK® (RoHS compliant) March 2010 2 Mbit, low voltage, Serial Flash memory with 75 MHz SPI bus interface Rev 14 M25P20 SO8 (MN) 150 mils width QFN8L (MS) MLP8 VFQFPN8 (MP) (MLP8 mm) 1/55 www.Numonyx.com ...
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... Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . .11 4.4 Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . .11 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.6 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.7 Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR) ...
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Read Data Bytes (READ ...
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... List of tables Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 5. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8. Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 10. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 11 ...
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... List of figures Figure 1. Logic Diagram Figure 2. SO and MLP8 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. Bus Master and memory devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Disable (WRDI) Instruction Sequence Figure 9 ...
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... Summary description The M25P20 Mbit (256K x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25P20 features high performance instructions allowing clock frequency operation MHz The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction ...
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... PCB. 2. See Package mechanical section for package dimensions, and how to identify pin-1. Table 1. Signal Names C Serial Clock D Serial Data Input Q Serial Data Output S Chip Select W Write Protect HOLD Hold V Supply Voltage CC V Ground SS M25P20 HOLD AI04081B , SS 7/55 ...
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... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). ...
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... The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate. 2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high- impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (e ...
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Figure 4. SPI modes supported CPOL CPHA 10/55 MSB MSB AI01438B ...
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... Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P20 features the following data protection mechanisms: Power On Reset and an internal timer (t inadvertant changes while the power supply is outside the operating specification. ...
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... If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. Memory Content Protected Area none Upper quarter (Sector 3) ...
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Figure 5. Hold Condition Activation C HOLD 14/55 Hold Condition (standard use) (non-standard use) Hold Condition AI02029D ...
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... Memory organization The memory is organized as: 262,144 bytes (8 bits each) 4 sectors (512 Kbits, 65536 bytes each) 1024 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...
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... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. ...
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Table 4. Instruction Set Instruction WREN Write Enable WRDI Write Disable (1) RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes Read Data Bytes at Higher FAST_READ Speed PP Page Program SE Sector Erase ...
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Write Disable (WRDI) The Write Disable (WRDI) instruction The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The Write Enable Latch (WEL) bit is ...
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... Device identification (2 bytes) A Unique ID code (UID) (17 bytes, of which 16 available upon customer request). The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (12h). ...
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... The status and control bits of the Status Register are as follows: 6.4.1 WIP bit The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset such cycle is in progress. ...
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... Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set ...
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Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable ...
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... Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware protected against data modification ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... The instruction sequence is shown in The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely ...
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... Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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Figure 14. Page Program (PP) Instruction Sequence Instruction Data Byte ...
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Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction ...
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Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the ...
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Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the ...
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... Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic Signature, whose value for the M25P20 is 11h. Except while an Erase, Program or Write Status Register cycle is in progress, the Release ...
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... C Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P20, is 11h. Figure 19. Release from Deep Power-down (RES) Instruction Sequence Instruction D High Impedance Q Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time ...
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Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay ...
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Figure 20. Power-up Timing (max (min) Reset State of the Device V WI Table 8. Power-Up Timing and V Symbol ( (min low VSL CC (1) t Time delay to ...
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... V Electrostatic Discharge voltage (Human Body model) ESD 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the Numonyx ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. The minimum voltage may reach the value for no more than 20 ns during transitions; The maximum voltage may reach the value JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the ...
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Table 13. DC Characteristics (Device Grade 6) Symbol Parameter I Input Leakage Current LI Output Leakage I LO Current I Grade 6 CC1, Standby Current I Grade 3 CC1, I Grade 6 Deep Power-down CC2, Current I Grade 3 CC2, ...
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Table 14. DC Characteristics (Device Grade 3) Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Deep Power-down Current CC2 I Operating Current (READ) CC3 I Operating Current (PP) CC4 I Operating ...
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Table 17. Instruction Times (Device Grade 3) Test conditions specified in Symbol Alt. t Write Status Register Cycle Time W Page Program Cycle Time (256 Bytes) ( Page Program Cycle Time (n Bytes) t Sector Erase Cycle Time ...
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Table 19. AC Characteristics (25MHz Operation, Device Grade Symbol Alt ( CLH ( CLL (2) t CLCH (2) t CHCL t t SLCH CSS t ...
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Table 20. AC Characteristics (40MHz Operation, Device Grade 6) 40MHz available for products marked since week 20 of 2004, only Test conditions specified in Symbol Alt. Clock Frequency for the following f f instructions: FAST_READ, PP, SE, BE ...
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It is 30µs in devices produced with the “X” process technology. Details of how to find the process letter on the device marking are given in the Application note AN1995. Table 21. AC Characteristics (50MHz Operation, Device Grade 6) ...
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Value guaranteed by characterization, not 100% tested in production. 5. Expressed as a slew-rate. 6. Only applicable as a constraint for a WRSR instruction ...
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Table 22. AC characteristics, grade 2.7 V (continued) Applies only to products made with T9HX technology, identified with process digit ‘4’ Symbol Alt. S High to Standby mode without Read Elec- (5) t RES1 tronic Signature S ...
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Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL High Impedance Q Figure 24. Hold Timing HOLD tHLCH tCHHL tCHHH tHLQZ tHHQX tSHWL AI07439 tHHCH AI02032 45/55 ...
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Figure 25. Output Timing S C tCLQV tCLQX tCLQX Q ADDR. D LSB IN 46/55 tCH tCLQV tCL tQLQH tQHQL tSHQZ LSB OUT AI01449e ...
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Package mechanical Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline Drawing is not to scale. 2. The ‘1’ that appears in the top view of the package shows ...
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Figure 27. QFN8L (MLP8) 8-lead, dual flat package no lead, 6 × 5 mm, package outline Drawing is not to scale. Table 24. QFN8L (MLP8) 8-lead dual flat package no lead ...
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Figure 28. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Dual Flat Package No lead, 6x5mm, Package Outline Drawing is not to scale. 2. The circle in the top view of the package indicates ...
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... Numonyx Sales Office. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. 50/55 M25P20 – V (4) . ...
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... Tested Parts from the non Auto Tested parts). Note: Numonyx strongly recommends the use of the Automotive Grade devices (Auto Grade 6 and automotive envirnoment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your Numonyx sales office for a copy. M25P20 – ...
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... Changes Document written Serial Paged Flash Memory renamed as Serial Flash Memory Changes to text: Signal Description/Chip Select; Hold Condition/1st para; Protection modes; Release from Power-down and Read Electronic Signature (RES); Power-up Repositioning of several tables and illustrations without changing their contents Power-up timing illustration ...
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... SO8 Narrow package specifications updated (see Table 23). 10-Dec-2008 11 Applied Numonyx branding. Changed frequency up to 75MHz (only in the standard Vcc range). Added new package. 12-Oct-2008 12 Added UID/CFD protection. Extended Vcc range to 2.3 V. Created separate order information for standard parts and automotive ...
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... NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility Numonyx may make changes to specifications and product descriptions at any time, without notice. ...