M25P20 STMicroelectronics, M25P20 Datasheet
M25P20
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M25P20 Summary of contents
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... JEDEC Standard two-Byte Signature (2012h) – RES Instruction, One-Byte, Signature (11h), for backward compatibility Packages – ECOPACK® (RoHS compliant) June 2006 2 Mbit, low voltage, Serial Flash memory with 50MHz SPI bus interface Rev 10 M25P20 SO8 (MN) 150 mil width VFQFPN8 (MP) (MLP8) 1/50 www.st.com 1 ...
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... Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . 11 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.6 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.7 Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Write Status Register (WRSR 2/50 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 M25P20 ...
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... M25P20 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Page Program (PP 6.9 Sector Erase (SE 6.10 Bulk Erase (BE 6.11 Deep Power-down (DP 6.12 Release from Deep Power-down and Read Electronic Signature (RES Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters ...
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... AC Characteristics (50MHz Operation, Device Grade Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 22. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6x5mm, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 23. Ordering Information Scheme Table 24. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4/50 M25P20 ...
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... M25P20 List of figures Figure 1. Logic Diagram Figure 2. SO and VFQFPN Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Bus Master and memory devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. Write Disable (WRDI) Instruction Sequence Figure 9 ...
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... Summary description 1 Summary description The M25P20 Mbit (256K x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 4 sectors, each containing 256 pages. Each page is 256 bytes wide ...
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... M25P20 Table 1. Signal Names HOLD Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground Summary description 7/50 ...
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... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). 8/50 M25P20 ...
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... M25P20 3 SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). ...
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... SPI modes Figure 4. SPI modes supported CPOL CPHA 10/50 MSB M25P20 MSB AI01438B ...
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... M25P20 4 Operating features 4.1 Page Programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P20 features the following data protection mechanisms: Power On Reset and an internal timer (t changes while the power supply is outside the operating specification. ...
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... M25P20 Table 2. Protected Area Sizes Status Register Content BP1 Bit BP0 Bit The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) are 0. 4.7 Hold Condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence ...
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... Operating features Figure 5. Hold Condition Activation C HOLD 14/50 Hold Condition (standard use) M25P20 Hold Condition (non-standard use) AI02029D ...
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... M25P20 5 Memory organization The memory is organized as: 262,144 bytes (8 bits each) 4 sectors (512 Kbits, 65536 bytes each) 1024 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. ...
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... Chip Select (S) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. 16/50 Table 4. M25P20 ...
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... M25P20 Table 4. Instruction Set Instruction WREN Write Enable WRDI Write Disable (1) RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes Read Data Bytes at Higher FAST_READ Speed PP Page Program SE Sector Erase BE Bulk Erase DP Deep Power-down Release from Deep Power- ...
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... Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Figure 8. Write Disable (WRDI) Instruction Sequence 18/50 (Figure 8) resets the Write Enable Latch (WEL) bit Instruction D High Impedance Q M25P20 AI03750D ...
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... M25P20 6.3 Read Identification (RDID) The Read Identification (RDID) instruction is available in products with Process Technology code X only. The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (12h) ...
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... Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. 20/ Figure 10. BP1 BP0 WEL Block Protect Bits Write Enable Latch Bit Write In Progress Bit Table 2) becomes protected M25P20 b0 WIP ...
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... M25P20 Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence High Impedance Instruction Status Register Out MSB Instructions Status Register Out MSB 7 AI02031E 21/50 ...
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... Figure 11. Write Status Register (WRSR) Instruction Sequence 22/50 Figure 11. Table 2. The Write Status Register (WRSR) instruction also allows the Instruction High Impedance MSB Status Register AI02282D M25P20 ) is W ...
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... M25P20 Table 7. Protection Modes W SRWD Signal Bit Software Protected 1 1 Hardware 0 1 Protected 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial ...
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... High Impedance Q 1. Address bits A23 to A18 are Don’t Care. 24/50 Figure 12 Instruction 24-Bit Address MSB Data Out MSB M25P20 7 AI03748D ...
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... M25P20 6.7 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...
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... Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP1, BP0) bits (see 26/50 Figure 14. and Table 16: Instruction Times (Device Grade Table 3 and Table 2) is not executed. M25P20 Instruction Times 3)). ...
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... M25P20 Figure 14. Page Program (PP) Instruction Sequence MSB 1. Address bits A23 to A18 are Don’t Care Instruction 24-Bit Address MSB Data Byte 2 Data Byte 3 ...
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... Address bits A23 to A18 are Don’t Care. 28/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 15. Table 3 and Table 2) is not executed Instruction 23 22 MSB Bit Address AI03751D M25P20 ) is SE ...
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... M25P20 6.10 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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... Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 17. Deep Power-down (DP) Instruction Sequence 30/50 13). Figure 17 Instruction CC1 before the supply current is reduced Stand-by Mode Deep Power-down Mode M25P20 CC2 AI03753D ...
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... Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic Signature, whose value for the M25P20 is 11h. Except while an Erase, Program or Write Status Register cycle is in progress, the Release ...
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... C Instruction D High Impedance Q 1. The value of the 8-bit Electronic Signature, for the M25P20, is 11h. Figure 19. Release from Deep Power-down (RES) Instruction Sequence High Impedance Q Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, ...
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... M25P20 7 Power-up and Power-down At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied (min) at Power-up, and then for a further delay Power-down SS Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper Power-up and Power-down ...
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... V WI Write Inhibit Voltage (Device grade 3) 1. These parameters are characterized only. 34/50 Program, Erase and Write Commands are Rejected by the Device Chip Selection Not Allowed tVSL tPUW Threshold WI Parameter M25P20 Read Access allowed Device fully accessible time AI04009C Min. Max ...
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... M25P20 8 Initial delivery state The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). 9 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device ...
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... Sampled only, not 100% tested 36/50 Parameter Condition Device Grade 6 Device Grade 3 at 55°C Parameter Test Condition V OUT V IN =25°C and a frequency of 20MHz. A Min. Max. 2.7 3.6 –40 85 –40 125 Min. Max. 100,000 10,000 20 Min. Max M25P20 Unit V °C Unit cycles per sector years Unit pF pF ...
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... M25P20 Table 13. DC Characteristics (Device Grade 6) Symbol I Input Leakage Current LI I Output Leakage Current LO I Standby Current CC1 I Deep Power-down Current CC2 I Operating Current (READ) CC3 I Operating Current (PP) CC4 I Operating Current (WRSR) CC5 I Operating Current (SE) CC6 I Operating Current (BE) CC7 V Input Low Voltage ...
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... open – 0.5 0. – –100 A 0.2 Table 10 and Table 17 Min. Typ. Max. 5 1.4 0.4+ n*1/256 0.8 2.5 M25P20 (1) Unit ± 2 µA ± 2 µA 100 µA 50 µ +0 0 Unit 15 ms ...
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... M25P20 Table 16. Instruction Times (Device Grade 3) Symbol Alt ( 85°C 2. Preliminary data. 3. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one sequence including all the Bytes versus several sequences of only a few Bytes 256) Table 17 ...
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... HOLD Hold Time (relative to C) HOLD to Output Low-Z HOLD to Output High-Z Write Protect Setup Time Write Protect Hold Time S High to Deep Power-down Mode S High to Standby Mode without Electronic Signature Read S High to Standby Mode with Electronic Signature Read C M25P20 and Table 17 Min. Typ. Max. Unit D.C. 25 MHz D.C. ...
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... M25P20 Table 19. AC Characteristics (40MHz Operation, Device Grade 6) 40MHz available for products marked since week 20 of 2004, only Symbol Alt ( CLH ( CLL (3) t CLCH (3) t CHCL t t SLCH CSS t CHSL t t DVCH DSU t t CHDX ...
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... HOLD to Output Low-Z HOLD to Output High-Z Write Protect Setup Time Write Protect Hold Time S High to Deep Power-down Mode S High to Standby Power mode without Electronic Signature Read S High to Standby Power mode with Electronic Signature Read C M25P20 (1) and Table 17 Min. Typ. Max. Unit D.C. 50 MHz D ...
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... M25P20 Figure 22. Serial Input Timing S tCHSL C tDVCH D Q Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL High Impedance Q tSLCH tCHDX tCLCH MSB IN High Impedance DC and AC parameters tSHSL tCHSH tSHCH tCHCL LSB IN AI01447C tSHWL AI07439 43/50 ...
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... DC and AC parameters Figure 24. Hold Timing HOLD Figure 25. Output Timing S C tCLQV tCLQX tCLQX Q ADDR. D LSB IN 44/50 tHLCH tCHHL tCHHH tHLQZ tCH tCLQV tQLQH tQHQL M25P20 tHHCH tHHQX AI02032 tCL tSHQZ LSB OUT AI01449e ...
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... M25P20 11 Package mechanical Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline A2 1. Drawing is not to scale. 2. The ‘1’ that appears in the top view of the package shows the position of pin 1. Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, ...
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... 46/ millimeters Typ. Min. Max. 0.85 1.00 0.00 0.05 0.65 0.20 0.40 0.35 0.48 6.00 5.75 3.40 3.20 3.60 5.00 4.75 4.00 3.80 4.20 1.27 0.60 0.50 0.75 12° M25P20 VFQFPN-01 inches Typ. Min. Max. 0.0335 0.0394 0.0000 0.0020 0.0256 0.0079 0.0157 0.0138 0.0189 0.2362 0.2264 0.1339 0.1260 0.1417 0.1969 0.1870 0.1575 0.1496 0.1654 0.0500 0.0236 0.0197 0.0295 12° ...
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... ST Sales Office. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Part numbering M25P20 – (2) . ...
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... Notes removed from Table 23: Ordering Information 5.0 changes. End timing line of t Updated Page Program (PP) instructions in 6.0 Program (PP), Instruction Times (Device Grade 6) (Device Grade 3). Changes ; DC Characteristics/V IO CC3 Scheme. Small text modified in Figure 25: Output SHQZ Page Programming, and Instruction Times M25P20 (max), Timing. Page ...
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... M25P20 Table 24. Document revision history (continued) Date Revision 01-Dec-2005 22-Dec-2005 14-Apr-2006 05-Jun-2006 50MHz operation added (see Operation, Device Grade removed from under Plating Technology Scheme. MLP package renamed as VFQFPN, silhouette and package 7.0 mechanical drawing updated (see package silhouette Figure 27: VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6x5mm, Package 26 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 50/50 Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com M25P20 ...