M25P20-VMN6 NUMONYX, M25P20-VMN6 Datasheet
M25P20-VMN6
Specifications of M25P20-VMN6
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M25P20-VMN6 Summary of contents
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... SPI Bus Compatible Serial Interface 40MHz Clock Rate (maximum) Deep Power-down Mode 1 A (typical) Electronic Signature (11h) August 2005 2 Mbit, Low Voltage, Serial Flash Memory With 40MHz SPI Bus Interface Figure 1. Packages M25P20 8 1 SO8 (MN) 150 mil width VDFPN8 (MP) (MLP8) 1/40 ...
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... M25P20 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Serial Data Output ( Serial Data Input ( Serial Clock ( Chip Select ( Hold (HOLD Write Protect ( SPI MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Status Register ...
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... Release from Deep Power-down and Read Electronic Signature (RES POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 INITIAL DELIVERY STATE MAXIMUM RATING AND AC PARAMETERS PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 REVISION HISTORY M25P20 3/40 ...
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... M25P20 SUMMARY DESCRIPTION The M25P20 Mbit (256K x 8) Serial Flash Memory, with advanced write protection mecha- nisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 4 sectors, each con- taining 256 pages ...
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... Chip Select (S) driven Low. Write Protect (W). The main purpose of this in- put signal is to freeze the size of the area of mem- ory that is protected against program or erase instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). M25P20 5/40 ...
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... M25P20 SPI MODES These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data Figure 4 ...
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... Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits. M25P20 . CC1 . The device remains in this CC2 Table 5 ...
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... The environments where non-volatile memory de- vices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P20 features the following data protection mechanisms: Power On Reset and an internal timer (t can provide protection against inadvertant changes while the power supply is outside the operating specification ...
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... To restart commu- nication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. Hold Condition (standard use) M25P20 Figure Hold Condition (non-standard use) AI02029D 9/40 ...
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... M25P20 MEMORY ORGANIZATION The memory is organized as: 262,144 bytes (8 bits each) 4 sectors (512 Kbits, 65536 bytes each) 1024 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable ...
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... Status Register cycle, Program cycle or Erase cy- cle continues unaffected. One-byte Instruction Code 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 1101 1000 1100 0111 1011 1001 1010 1011 M25P20 Address Dummy Data Bytes Bytes Bytes 06h 0 0 04h 0 0 05h ...
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... M25P20 Write Enable (WREN) The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set pri every Page Program (PP), Sector Erase Figure 8. Write Enable (WREN) Instruction Sequence Write Disable (WRDI) The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit ...
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... Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) be- come read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for exe- cution Status Register Out MSB Status Register Out MSB AI02031E M25P20 Table 13/40 ...
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... M25P20 Write Status Register (WRSR) The Write Status Register (WRSR) instruction al- lows new values to be written to the Status Regis- ter. Before it can be accepted, a Write Enable (WREN) instruction must previously have been ex- ecuted. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL) ...
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... If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used. M25P20 Memory Content 1 1 Unprotected Area Ready to accept Page ...
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... M25P20 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the mem- ...
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... High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) in- struction, while an Erase, Program or Write cycle Figure 13 progress, is rejected without having any ef- fects on the cycle that is in progress BIT ADDRESS DATA OUT MSB Read Data Bytes at Higher 47 DATA OUT MSB MSB M25P20 Speed AI04006 17/40 ...
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... M25P20 Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been ex- ecuted. After the Write Enable (WREN) instruction has been decoded, the device sets the Write En- able Latch (WEL) ...
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... Figure 14. Page Program (PP) Instruction Sequence Instruction Data Byte MSB Note: Address bits A23 to A18 are Don’t Care 24-Bit Address MSB Data Byte MSB Data Byte MSB Data Byte 256 MSB AI04082B M25P20 19/40 ...
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... M25P20 Sector Erase (SE) The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decod- ed, the device sets the Write Enable Latch (WEL). ...
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... At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if both Block Protect (BP1, BP0) bits are 0. The Bulk Figure 16.. Erase (BE) instruction is ignored if one, or more, sectors are protected Instruction M25P20 AI03752D 21/40 ...
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... M25P20 Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest con- sumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions ...
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... Instruction D High Impedance Q Note: The value of the 8-bit Electronic Signature, for the M25P20, is 11h. Data Input (D) during the rising edge of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C) ...
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... M25P20 Figure 19. Release from Deep Power-down (RES) Instruction Sequence Instruction D High Impedance Q Driving Chip Select (S) High after the 8-bit instruc- tion byte has been received by the device, but be- fore the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in ure 19 ...
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... V (min) level CC CC Table 7.. , has elapsed, after V VSL CC (min), the device can be selected for CC delay is not yet PUW supply. Each de drops from the operat all operations are disabled WI Device fully accessible time M25P20 has risen rail decou- AI04009C 25/40 ...
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... M25P20 Table 7. Power-Up Timing and V Symbol 1 V (min low t CC VSL 1 Time delay to Write instruction t PUW 1 Write Inhibit Voltage V WI Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains ...
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... JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ). plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter 2 M25P20 Min. Max. Unit –65 150 °C 1 °C See note – ...
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... M25P20 DC AND AC PARAMETERS This section summarizes the operating and mea- surement conditions, and the DC and AC charac- teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de- rived from tests performed under the Measure- Table 9. Operating Conditions Symbol V Supply Voltage ...
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... –100 A OH Test Condition (in addition to those in Table 9 0.1V / 0.9.V at 40MHz open C = 0.1V / 0.9.V at 20MHz open 1 –100 A OH M25P20 Min. Max. Unit ± 2 µA ± 2 µA 50 µA 5 µ – 0.5 0. 0. –0 Unit Min. Max. ± 2 µA ± 2 µA 100 µA 50 µ ...
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... M25P20 Table 14. Instruction Times (Device Grade 6) Test conditions specified in Symbol Alt. t Write Status Register Cycle Time W Page Program Cycle Time (256 Bytes) ( Page Program Cycle Time (n Bytes) t Sector Erase Cycle Time SE t Bulk Erase Cycle Time BE 1. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one se- quence including all the Bytes versus several sequences of only a few Bytes ...
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... HHCH t HOLD Hold Time (relative to C) CHHL 2 t HOLD to Output Low HHQX Input and Output Timing Reference Levels Table 9. and Table 16. Parameter 3 (peak to peak) 3 (peak to peak) M25P20 0.7V CC 0.5V CC 0.3V CC AI07455 Min. Typ. Max. Unit D.C. 25 MHz D.C. 20 MHz 0.1 V/ns ...
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... M25P20 Test conditions specified in Symbol Alt HOLD to Output High HLQZ 4 Write Protect Setup Time t WHSL 4 Write Protect Hold Time t SHWL 2 S High to Deep Power-down Mode High to Standby Mode without Electronic 2 t RES1 Signature Read S High to Standby Mode with Electronic 2 t RES2 Signature Read Note: 1 ...
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... Details of how to find the date of marking are given in Application Note, AN1995. Figure 22. Serial Input Timing S tCHSL C tDVCH D High Impedance Q Table 9. Parameter C tSLCH tCHSH tCHDX tCLCH MSB IN 5 and Table 16. Min. Typ. Max 100 3 3 1.8 tSHSL tSHCH tCHCL LSB IN AI01447C M25P20 Unit 33/40 ...
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... M25P20 Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL High Impedance Q Figure 24. Hold Timing HOLD 34/40 tHLCH tCHHL tCHHH tHLQZ tHHQX tSHWL AI07439 tHHCH AI02032 ...
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... Figure 25. Output Timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tCH tCLQV tQLQH tQHQL M25P20 tCL tSHQZ LSB OUT AI01449e 35/40 ...
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... M25P20 PACKAGE MECHANICAL Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline SO-a Note: Drawing is not to scale. Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data Symbol Typ 1. 36/ millimeters Min ...
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... D2 L VDFPN-01 inches Typ. Min. 0.0335 0.0394 0.0000 0.0020 0.0256 0.0079 0.0157 0.0138 0.0189 0.2362 0.2264 0.1339 0.1260 0.1417 0.1969 0.1870 0.1575 0.1496 0.1654 0.0500 0.0236 0.0197 0.0295 M25P20 Max. 12° 37/40 ...
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... Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. Device grade 3 available in SO8 Lead-free and RoHS compliant package For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 38/40 M25P20 – ...
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... Instruction Times (Device Grade 6) Description of Revision ; DC Characteristics/V IO (max) modified. W Table 21., Ordering Information modified in Figure 25., Output SHQZ Page and Instruction Times (Device Grade and clock slew WI CC3 (max), t (typ) and t CC3 SE Scheme. Small text changes. End Timing. Programming, Page Program (PP), 3). M25P20 (typ) BE 39/40 ...
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... M25P20 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...