LCMXO2280C-3FT324I LATTICE SEMICONDUCTOR, LCMXO2280C-3FT324I Datasheet - Page 16

• Manufacturer Part Number: LCMXO2280C-3FT324I
• Description: CPLD MachXO Family 1140 Macro Cells 1.8V/2.5V/3.3V 324-Pin FTBGA Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LCMXO2280C-3FT324I

• Package: 324FTBGA
• Family Name: MachXO
• Number Of Macro Cells: 1140
• Maximum Propagation Delay Time: 5.1 ns
• Number Of User I/os: 271
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Ram Bits: 28262.4
• Memory Type: SRAM
• Operating Temperature: -40 to 100 °C

Lattice Semiconductor
Figure 2-13. Memory Core Reset
For further information on the sysMEM EBR block, see the details of additional technical documentation at the end
of this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-14. The GSR input to the
EBR is always asynchronous.
Figure 2-14. EBR Asynchronous Reset (Including GSR) Timing Diagram
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/f
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR sig-
nal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-14. The reset timing
rules apply to the RPReset input vs the RE input and the RST input vs. the WE and RE inputs. Both RST and
RPReset are always asynchronous EBR inputs.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled
GSRN
RSTA
RSTB
Programmable Disable
Reset
Clock
Clock
Enable
Memory Core
2-13
Output Data
L
L
D
D
Latches
CLR
CLR
SET
SET
Q
Q
MachXO Family Data Sheet
Port A[17:0]
Port B[17:0]
MAX
(EBR clock). The reset
Architecture