M4-128N/64-15JC LATTICE SEMICONDUCTOR, M4-128N/64-15JC Datasheet - Page 19

• Manufacturer Part Number: M4-128N/64-15JC
• Description: CPLD MACH 4 Family 5K Gates 128 Macro Cells 41.7MHz/55.6MHz EECMOS Technology 5V 84-Pin PLCC Tube
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of M4-128N/64-15JC

• Package: 84PLCC
• Family Name: MACH 4
• Device System Gates: 5000
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 64
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 41.7|55.6 MHz
• Number Of Product Terms Per Macro: 20
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged,
providing flexibility. In asynchronous mode (Figure 8), a single individual product term is
provided for initialization. It can be selected to control reset or preset.
Note that the reset/preset swapping selection feature effects power-up reset as well. The
initialization functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data
to the output switch matrix and the input switch matrix. The output switch matrix can route this
data to an output if so desired. The input switch matrix can send the signal back to the central
switch matrix as feedback.
Note:
1. Transparent latch is unaffected by AR, AP
Product Term
Individual
Reset
Power-Up
a. Reset
Reset
Figure 8. Asynchronous Mode Initialization Configurations
AR
D/L/T
0
0
1
1
Table 9. Asynchronous Reset/Preset Operation
AP
AR
Q
17466G-014
AP
0
1
0
1
MACH 4 Family
Product Term
CLK/LE
Individual
X
X
X
X
Preset
1
Power-Up
See Table 8
Preset
Q+
1
0
0
b. Preset
D/L/T
AP
AR
17466G-015
Q
13