XC3S250E-4TQ144C Xilinx Inc, XC3S250E-4TQ144C Datasheet - Page 203

• Manufacturer Part Number: XC3S250E-4TQ144C
• Description: FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC3S250E-4TQ144C

• Package: 144TQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 5508
• Device Logic Units: 612
• Device System Gates: 250000
• Number Of Registers: 4896
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 108
• Ram Bits: 221184

FG320: 320-ball Fine-pitch Ball Grid Array
The 320-ball fine-pitch ball grid array package, FG320, sup-
ports three different Spartan-3E FPGAs, including the
XC3S500E, the XC3S1200E, and the XC3S1600E, as
shown in
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
Table 148
bank number and then by pin name of the largest device.
Pins that form a differential I/O pair appear together in the
table. The table also shows the pin number for each pin and
the pin type, as defined earlier.
The highlighted rows indicate pinout differences between
the XC3S500E, the XC3S1200E, and the XC3S1600E
FPGAs. The XC3S500E has 18 unconnected balls, indi-
cated as N.C. (No Connection) in
black diamond character ( ) in
Pinout Table
Table 148: FG320 Package Pinout
DS312-4 (v3.8) August 26, 2009
Product Specification
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 148
lists all the package pins. They are sorted by
R
IP
IO
IO
N.C. ( )
IO
IP
IO
IO
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
XC3S500E Pin Name
and
Figure
87.
Table 148
Table 148
IO
IO
IO
IO
IO
IO
IO
IO
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
and
XC3S1200E Pin Name
and with the
Figure
www.xilinx.com
87.
If the table row is highlighted in tan, then this is an instance
where an unconnected pin on the XC3S500E FPGA maps
to a VREF pin on the XC3S1200E and XC3S1600E FPGA.
If the FPGA application uses an I/O standard that requires a
VREF voltage reference, connect the highlighted pin to the
VREF voltage supply, even though this does not actually
connect to the XC3S500E FPGA. This VREF connection on
the board allows future migration to the larger devices with-
out modifying the printed-circuit board.
All other balls have nearly identical functionality on all three
devices.
migration differences for the FG320 package.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at:
http://www.xilinx.com/support/documentation/data_sheets/s3e_pin.zip
IO
IO
IO
IO
IO
IO
IO
IO
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L05N_0/VREF_0
IO_L05P_0
IO_L06N_0
IO_L06P_0
XC3S1600E Pin Name
Table 147
summarizes the Spartan-3E footprint
FG320
Ball
D13
C14
D14
A11
A12
E13
B11
A16
B16
A14
B14
B13
A13
E12
F12
C4
G9
A7
A8
Pinout Descriptions
500E: INPUT
500E: INPUT
500E: N.C.
1200E: I/O
1600E: I/O
1200E: I/O
1600E: I/O
1200E: I/O
1600E: I/O
VREF
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
203