XC3S250E-4TQ144C Xilinx Inc, XC3S250E-4TQ144C Datasheet - Page 48

• Manufacturer Part Number: XC3S250E-4TQ144C
• Description: FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 144-Pin TQFP
• Manufacturer: Xilinx Inc

Specifications of XC3S250E-4TQ144C

• Package: 144TQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 5508
• Device Logic Units: 612
• Device System Gates: 250000
• Number Of Registers: 4896
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 108
• Ram Bits: 221184

Functional Description
Digital Clock Managers (DCMs)
For additional information, refer to the Using Digital Clock
Managers (DCMs) chapter in UG331.
Differences from the Spartan-3 Architecture
•
•
•
Overview
Spartan-3E FPGA Digital Clock Managers (DCMs) provide
flexible, complete control over clock frequency, phase shift
and skew. To accomplish this, the DCM employs a
Delay-Locked Loop (DLL), a fully digital control system that
uses feedback to maintain clock signal characteristics with a
high degree of precision despite normal variations in oper-
ating temperature and voltage. This section provides a fun-
damental description of the DCM.
The XC3S100E FPGA has two DCMs, one at the top and
one at the bottom of the device. The XC3S250E and
XC3S500E FPGAs each include four DCMs, two at the top
and two at the bottom. The XC3S1200E and XC3S1600E
FPGAs contain eight DCMs with two on each edge (see
also
rounded by CLBs within the logic array and is no longer
48
Spartan-3E FPGAs have two, four, or eight DCMs,
depending on device size.
The variable phase shifting feature functions differently
on Spartan-3E FPGAs than from Spartan-3 FPGAs.
The Spartan-3E DLLs support lower input frequencies,
down to 5 MHz. Spartan-3 DLLs support down to
18 MHz.
Figure
45). The DCM in Spartan-3E FPGAs is sur-
PSINCDEC
PSCLK
CLKFB
CLKIN
PSEN
RST
Figure 40: DCM Functional Blocks and Associated Signals
DLL
Status
DCM
Shifter
Phase
Logic
www.xilinx.com
DFS
located at the top and bottom of a column of block RAM as
in the Spartan-3 architecture. The Digital Clock Manager is
instantiated within a design using a “DCM” primitive.
The DCM supports three major functions:
•
•
•
Although a single design primitive, the DCM consists of four
interrelated functional units: the Delay-Locked Loop (DLL),
the Digital Frequency Synthesizer (DFS), the Phase Shifter
(PS), and the Status Logic. Each component has its associ-
ated signals, as shown in
8
Clock-skew Elimination: Clock skew within a system
occurs due to the different arrival times of a clock signal
at different points on the die, typically caused by the
clock signal distribution network. Clock skew increases
setup and hold time requirements and increases
clock-to-out times, all of which are undesirable in high
frequency applications. The DCM eliminates clock
skew by phase-aligning the output clock signal that it
generates with the incoming clock signal. This
mechanism effectively cancels out the clock distribution
delays.
Frequency Synthesis: The DCM can generate a wide
range of different output clock frequencies derived from
the incoming clock signal. This is accomplished by
either multiplying and/or dividing the frequency of the
input clock signal by any of several different factors.
Phase Shifting: The DCM provides the ability to shift
the phase of all its output clock signals with respect to
the input clock signal.
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
PSDONE
CLK0
CLKFX
CLKFX180
LOCKED
STATUS [7:0]
Distribution
Clock
Delay
DS099-2_07_101205
Figure
DS312-2 (v3.8) August 26, 2009
40.
Product Specification
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