XC3S250E-4VQG100I Xilinx Inc, XC3S250E-4VQG100I Datasheet - Page 132

• Manufacturer Part Number: XC3S250E-4VQG100I
• Description: FPGA Spartan®-3E Family 250K Gates 5508 Cells 572MHz 90nm (CMOS) Technology 1.2V 100-Pin VTQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S250E-4VQG100I

• Package: 100VTQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 5508
• Device Logic Units: 612
• Device System Gates: 250000
• Number Of Registers: 4896
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 66
• Ram Bits: 221184
• Package / Case: 100-TQFP, 100-VQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 66
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DC and Switching Characteristics
Table 93: Timing for the IOB Three-State Path
132
Notes:
1.
2.
3.
Synchronous Output Enable/Disable Times
T
T
Asynchronous Output Enable/Disable Times
T
Set/Reset Times
T
T
IOCKHZ
IOCKON
GTS
IOSRHZ
IOSRON
Symbol
The numbers in this table are tested using the methodology presented in
Table 77
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from
For minimum delays use the values reported by the Timing Analyzer.
(2)
(2)
and
Table
Time from the active transition at the OTCLK
input of the Three-state Flip-Flop (TFF) to
when the Output pin enters the
high-impedance state
Time from the active transition at TFF’s
OTCLK input to when the Output pin drives
valid data
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3E
primitive to when the Output pin enters the
high-impedance state
Time from asserting TFF’s SR input to when
the Output pin enters a high-impedance state
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
80.
Description
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Table
LVCMOS25,
12 mA output
drive, Fast slew
rate
LVCMOS25,
12 mA output
drive, Fast slew
rate
LVCMOS25,
12 mA output
drive, Fast slew
rate
Table 95
Conditions
94.
and are based on the operating conditions set forth in
Device
All
All
All
All
All
DS312-3 (v3.8) August 26, 2009
Speed Grade
Max
1.49
2.70
8.52
2.11
3.32
-5
Product Specification
Max
1.71
3.10
9.79
2.43
3.82
-4
Units
ns
ns
ns
ns
ns
R