XC5VLX50T-1FF1136C Xilinx Inc, XC5VLX50T-1FF1136C Datasheet - Page 101

• Manufacturer Part Number: XC5VLX50T-1FF1136C
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FF1136C

• Package: 1136FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 480
• Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
PLL Clock Input Signals
PLLs in the bottom half of the Virtex-5 device are driven by the global clock pins in bank4
and can be paired as listed in
Table 3-7: PLLs in the Bottom Half Pairing
Other important notes on these pairings:
•
•
•
The PLL clock source can come from several sources including:
•
•
•
•
The pin description names do not contain other possible multipurpose functions such
as _CC, _VRN, _VRP or _VREF.
Only the P-side pins are shown. For differential clock connections use the equivalent
N-side pin. Inside the FPGA, only the P-side of the differential pin pair can connect to
the CMT.
For a mapping to the actual pin numbers consult the Virtex-5 Family Packaging
Specifications.
IBUFG - Global clock input buffer, the PLL will compensate the delay of this path.
BUFGCTRL - Internal global clock buffer, the PLL will not compensate the delay of
this path.
IBUF - Not recommended since the PLL can not compensate for the delay of the
general route. An IBUF clock input must route to a BUFG before routing to a PLL.
DCMOUT - Any DCM output to PLL will compensate the delay of this path.
IO_L9P_GC_4
IO_L8P_GC_4
IO_L7P_GC_4
IO_L6P_GC_4
IO_L5P_GC_4
CLKIN1
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IO_L4P_GC_4
IO_L3P_GC_4
IO_L2P_GC_4
IO_L1P_GC_4
IO_L0P_GC_4
Table
CLKIN2
3-6.
General Usage Description
101