XC5VLX50T-1FF1136C Xilinx Inc, XC5VLX50T-1FF1136C Datasheet - Page 94

• Manufacturer Part Number: XC5VLX50T-1FF1136C
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FF1136C

• Package: 1136FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 480
• Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 480
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1136-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 122-1586 - BOARD EVAL FOR VIRTEX-5 ML555HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Chapter 3: Phase-Locked Loops (PLLs)
94
Jitter Filter
Limitations
VCO Operating Range
Minimum and Maximum Input Frequency
Duty Cycle Programmability
PLL outputs are programmed to provide a 533 MHz PowerPC® processor clock, a
266 MHz PowerPC processor gasket clock, a 178 MHz clock, a 133 MHz memory interface
clock, a 66 MHz PCI™ clock, and a 33 MHz PCI clock. In this example, there are no
required phase relationships between the reference clock and the output clocks, but there
are required relationships between the output clocks.
X-Ref Target - Figure 3-5
PLLs always reduce the jitter inherent on a reference clock. The PLL can be instantiated as
a standalone function to simply support filtering jitter from an external clock before it is
driven into the another block (including the DCM). As a jitter filter, it is usually assumed
that the PLL acts as a buffer and regenerates the input frequency on the output (e.g.,
F
PLL attribute BANDWIDTH set to Low. Setting the BANDWIDTH to Low can incur an
increase in the static offset of the PLL.
The PLL has some restrictions that must be adhered to. These are summarized in the PLL
electrical specification in the Virtex-5 FPGA Data Sheet. In general, the major limitations are
VCO operation range, input frequency, duty cycle programmability, and phase shift.
The minimum and maximum VCO operating frequencies are defined in the electrical
specification of the Virtex-5 FPGA Data Sheet. These values can also be extracted from the
speed specification.
The minimum and maximum CLKIN input frequency are defined in the electrical
specification of the Virtex-5 FPGA Data Sheet.
Only discrete duty cycles are possible given a VCO operating frequency. The counter
settings to determine the output duty cycle is further discussed under
IN
Reference
= 100 MHz, F
33 MHz
Clock
OUT
Figure 3-5: PLL as a Frequency Synthesizer
= 100 MHz). In general, greater jitter filtering is possible by using the
www.xilinx.com
D = 1
PFD, CP,
LF, VCO
M = 16
D0 = 1
D0 = 2
D0 = 3
D0 = 4
D0 = 8
D = 16
PowerPC Processor Core
PowerPC Processor Gasket
CLB/Fabric
Memory Interface
PCI-66
PCI-33
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Counter
UG190_3_05_111808
Control.