XC6SLX100-2FGG484C Xilinx Inc, XC6SLX100-2FGG484C Datasheet - Page 51

• Manufacturer Part Number: XC6SLX100-2FGG484C
• Description: FPGA Spartan®-6 Family 101261 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXr

Specifications of XC6SLX100-2FGG484C

• Package: 484FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 101261
• Device Logic Units: 63288
• Number Of Registers: 126576
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 326
• Ram Bits: 4939776
• Number Of Logic Elements/cells: 101261
• Number Of Labs/clbs: 7911
• Total Ram Bits: 4939776
• Number Of I /o: 326
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• No. Of Logic Blocks: 15822
• No. Of Macrocells: 101261
• Family Type: Spartan-6
• No. Of Speed Grades: 2
• No. Of I/o's: 326
• Clock Management: DCM, PLL
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 52: Switching Characteristics for the Delay-Locked Loop (DLL)
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Output Frequency Ranges
CLKOUT_FREQ_CLK0
CLKOUT_FREQ_CLK90
CLKOUT_FREQ_2X
CLKOUT_FREQ_DV
Output Clock Jitter
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
Duty Cycle
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0,
Phase Alignment
CLKIN_CLKFB_PHASE
CLKOUT_PHASE_DLL
Symbol
(4)
(4)
(2)(3)(4)
Frequency for the CLK0 and
CLK180 outputs.
Frequency for the CLK90 and
CLK270 outputs.
Frequency for the CLK2X and
CLK2X180 outputs.
Frequency for the CLKDV output.
Period jitter at the CLK0 output.
Period jitter at the CLK90 output.
Period jitter at the CLK180 output.
Period jitter at the CLK270 output.
Period jitter at the CLK2X and
CLK2X180 outputs.
Period jitter at the CLKDV output
when performing integer division.
Period jitter at the CLKDV output
when performing non-integer
division.
CLK90, CLK180, CLK270, CLK2X,
CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock
tree duty-cycle distortion.
Phase offset between the CLKIN
and CLKFB inputs
(CLK_FEEDBACK = 1X).
Phase offset between the CLKIN
and CLKFB inputs
(CLK_FEEDBACK = 2X).
Phase offset between DLL outputs
for CLK0 to CLK2X (not CLK2X180).
Phase offset between DLL outputs
for all others.
Description
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
0.3125
Min
Maximum = ±[1% of CLKIN period + 150]
10
5
5
–
–
–
–
–
–
–
-3
Maximum = ±[0.5% of CLKIN period + 100]
Maximum = ±[0.5% of CLKIN period + 100]
±100
±150
±150
±150
±150
±150
±250
Max
280
200
375
186
Maximum = ±[1% of CLKIN period + 100]
Typical = ±[1% of CLKIN period + 350]
(1)
0.3125
Min
10
5
5
–
–
–
–
–
–
–
-3N
Speed Grade
±100
±150
±150
±150
±150
±150
±250
Max
280
200
375
186
0.3125
Min
10
5
5
–
–
–
–
–
–
–
-2
±100
±150
±150
±150
±150
±150
±250
Max
250
200
334
166
0.3125
period + 200]
Min
Maximum =
10
5
5
–
–
–
–
–
–
–
±[1% of
CLKIN
-1L
±100
±150
±150
±150
±150
±250
±350
Max
88.6
175
175
250
Units
MHz
MHz
MHz
MHz
Max
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
51