AD7495BRZ Analog Devices Inc, AD7495BRZ Datasheet - Page 18

• Manufacturer Part Number: AD7495BRZ
• Description: ADC Single SAR 1MSPS 12-Bit Serial 8-Pin SOIC N
• Manufacturer: Analog Devices Inc

Specifications of AD7495BRZ

• Package: 8SOIC N
• Resolution: 12 Bit
• Sampling Rate: 1000 KSPS
• Architecture: SAR
• Number Of Analog Inputs: 1
• Digital Interface Type: Serial (SPI, QSPI, Microwire)
• Input Type: Voltage
• Signal To Noise Ratio: 68 dB
• Polarity Of Input Voltage: Unipolar
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 10.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7475/AD7495
Full power-down is entered in a way similar to partial power-
down, except the timing sequence shown in Figure 20 must be
executed twice. The conversion process must be interrupted in a
similar fashion by bringing CS high anywhere after the second
falling edge of SCLK and before the tenth falling edge of SCLK.
The device enters partial power-down at this point. To reach
full power-down, the next conversion cycle must be interrupted
in the same way, as shown in Figure 22. Once CS has been
brought high in this window of SCLKs, then the part powers
down completely.
Note that it is not necessary to complete the 16 SCLKs once CS
has been brought high to enter a power-down mode.
To exit full power-down, and power up the AD7475/AD7495
again, a dummy conversion is performed as when powering up
from partial power-down. On the falling edge of CS , the device
begins to power up and continues to power up as long as CS is
held low until after the falling edge of the tenth SCLK. The
power-up time is longer than one dummy conversion cycle
however, and this time, t
conversion can be initiated, as shown in Figure 23. See the
Timing Specifications section for more information.
When power supplies are first applied to the AD7475/AD7495,
the ADC may power up in either of the power-down modes
or normal mode. Because of this, it is best to allow a dummy
cycle to elapse to ensure the part is fully powered up before
attempting a valid conversion. Likewise, if the intent is to keep
the part in partial power-down mode immediately after the
supplies are applied, then two dummy cycles must be initiated.
The first dummy cycle must hold CS low until after the tenth
SDATA
SCLK
CS
1
POWER-UP,
THE PART BEGINS
TO POWER UP
must elapse before a
INVALID DATA
10
Figure 23. Exiting Full Power-Down Mode
t
POWER-UP
16
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SCLK falling edge, as shown in Figure 19. In the second cycle,
CS must be brought high before the tenth SCLK edge, but
after the second SCLK falling edge, as shown in Figure 20.
Alternatively, if the intent is to place the part in full power-
down mode when the supplies have been applied, then three
dummy cycles must be initiated. The first dummy cycle must
hold CS low until after the tenth SCLK edge, as shown in
Figure 19; the second and third dummy cycle place the part in
full power-down, as shown in Figure 22. (See the Operating
Modes section.) Once supplies are applied to the AD7475,
enough time must be allowed for the external reference to
power up and charge the reference capacitor to its final value.
For the AD7495, enough time should be allowed for the
internal reference buffer to charge the reference capacitor. Then,
to place the AD7475/ AD7495 in normal mode, a dummy cycle,
1 μs, should be initiated. If the first valid conversion is then
performed directly after the dummy conversion, ensure that
adequate acquisition time has been allowed. As mentioned
earlier, when powering up from the power-down mode, the part
returns to track upon the first SCLK edge applied after the
falling edge of CS . However, when the ADC powers up initially
after supplies are applied, the track-and-hold is already in track.
This means (assuming one has the facility to monitor the ADC
supply current) if the ADC powers up in the desired mode of
operation, and a dummy cycle is not required to change mode,
then neither is a dummy cycle required to place the track-and-
hold into track. If no current monitoring facility is available, the
relevant dummy cycle(s) should be performed to ensure the
part is in the required mode.
1
THE PART IS FULLY
POWERED UP
VALID DATA
16