MAX2829ETN+T Maxim Integrated Products, MAX2829ETN+T Datasheet - Page 31

• Manufacturer Part Number: MAX2829ETN+T
• Description: RF Transceiver Dual-Band 802.11a-b- -g Transceivers WLAN
• Manufacturer: Maxim Integrated Products

Specifications of MAX2829ETN+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9. Register Default/SPI Reset Settings
Table 10. Standby Register
(A3:A0 = 0010)
Integer-Divider
Linearity/Base-
Lowpass Filter
DATA BIT
PA Bias DAC
Tx VGA Gain
Divider Ratio
Control/RSSI
Band Select
REGISTER
Calibration
Fractional-
band Gain
Register 0
Register 1
Standby
and PLL
Rx Gain
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Ratio
Rx
Tx
DEFAULT
D13
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
______________________________________________________________________________________
D12
1
0
1
1
1
1
1
0
0
0
0
0
0
MIMO Select. Set to 0 for normal
operation. Set to 1 for MIMO
applications.
Set to 1
Voltage Reference (Pin 23)
PA Bias DAC, in Tx Mode
Set to 0
Set to 1
D11
0
0
0
0
1
1
1
0
0
0
0
0
0
D10
DESCRIPTION
0
0
0
0
1
0
1
0
0
0
0
0
0
D9
0
0
0
0
0
0
0
0
0
1
1
0
0
Single-/Dual-Band 802.11a/b/g
D8
1
0
0
0
1
0
0
0
0
0
1
0
0
World-Band Transceiver ICs
DEFAULT
D7
0
1
0
1
1
0
0
0
0
0
1
0
0
D6
1
1
0
0
1
0
0
0
0
0
1
1
0
to the VCO drifting to an adjacent sub-band. In this
case, it is advisable to reprogram the PLL by either
manual or automatic sub-band selection.
The MAX2828/MAX2829 include 13 programmable, 18-
bit registers: 0, 1, standby, integer-divider ratio, frac-
tional-divider ratio, band select and PLL, calibration,
lowpass filter, Rx control/RSSI, Tx linearity/baseband
gain, PA bias DAC, Rx gain, and Tx VGA gain. The 14
most significant bits (MSBs) are used for register data.
The 4 least significant bits (LSBs) of each register con-
tain the register address. Data is shifted in MSB first.
The data sent to the devices, in 18-bit words, is framed
by CS. When CS is low, the clock is active and data is
shifted with the rising edge of the clock. When CS tran-
sitions high, the shift register is latched into the register
selected by the contents of the address bits. Only the
last 18 bits shifted into the device are retained in the
shift register. No check is made on the number of clock
pulses. For programming data words less than 14 bits
long, only the required data bits and the address bits
are required to be shifted, resulting in faster Rx and Tx
gain control where only the LSBs need to be pro-
D5
0
0
0
1
0
1
0
1
1
0
0
1
0
D4
0
0
0
0
1
0
0
0
0
0
0
1
0
D3
0
1
0
0
1
0
0
1
0
0
0
1
0
D2
0
0
1
0
1
1
0
0
1
0
0
1
0
Programmable Registers
D1
0
1
1
1
0
0
0
1
0
0
0
1
0
D0
0
0
1
0
1
0
0
0
1
0
0
1
0
ADDRESS
(A3:A0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
TABLE
10
11
12
13
14
15
16
17
18
19
20
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