MAX2829ETN+T Maxim Integrated Products, MAX2829ETN+T Datasheet - Page 37

• Manufacturer Part Number: MAX2829ETN+T
• Description: RF Transceiver Dual-Band 802.11a-b- -g Transceivers WLAN
• Manufacturer: Maxim Integrated Products

Specifications of MAX2829ETN+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 18. PA Bias DAC Register
(A3:A0 = 1010)
Table 19. Rx Gain Register
(A3:A0 = 1011)
DATA BIT
DATA BIT
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
DEFAULT
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
______________________________________________________________________________________
Set to 0
Sets PA bias DAC turn-on delay
after TXENA is set high and A3:A0
= 0010, D10 = 1, in steps of 0.5µs.
D9:D6 = 0001 corresponds to 0µs
and 1111 corresponds to 7µs.
Sets PA bias DAC output current in
steps of 5µA. D5:D0 = 000000
corresponds to 0µA and 111111
corresponds to 315µA.
Not Used. For faster Rx gain
setting, only D6:D0 need to be
programmed.
Rx LNA
Gain
Control
Rx VGA
Gain
Control
DESCRIPTION
DESCRIPTION
Rx baseband and RF
gain-control bits. D6
maps to digital input
pin B7 and D0 maps
to digital input pin B1.
D6:D0 = 0000000
corresponds to
minimum gain.
Single-/Dual-Band 802.11a/b/g
World-Band Transceiver ICs
This register controls the output current of the DAC,
which biases the external PA (see Table 18).
This register sets the Rx baseband and RF gain when
A3:A0 = 1000, D12 = 1 (see Table 19).
This register sets the Tx VGA gain when A3:A0 = 1001,
D10 = 1 (see Table 20).
The MAX2828/MAX2829 support multiple input multiple
output (MIMO) applications where multiple transceivers
are used in parallel. A special requirement for this appli-
cation is that all receivers must maintain a constant rela-
tive local oscillator phase, and that they continue to do so
after any receive-transmit-receive mode switching. The
same requirement holds for the transmitters—they should
all maintain a constant relative phase, and continue to do
so after any transmit-receive-transmit mode switching.
This feature is enabled in the MAX2828/MAX2829 by pro-
gramming A3:A0 = 0010, D13 = 1 and A3:A0 = 0101,
D13 = 1. The constant relative phases of the multiple
transceivers are maintained in the transmit, receive, and
standby modes of operation, as long as they are all using
a common external reference frequency source (crystal
oscillator).
Table 20. Tx VGA Gain Register
(A3:A0 = 1100)
DATA BIT
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PA Bias DAC Register Definition (A3:A0 = 1010)
Tx VGA Gain Register Definition (A3:A0 = 1100)
Rx Gain Register Definition (A3:A0 = 1011)
DEFAULT
Applications Information
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not Used. For faster Tx VGA gain
setting, only D5:D0 need to be
programmed.
Tx VGA Gain Control. D5 maps to
digital input pin B6 and D0 maps to
digital input pin B1. D5:D0 =
000000 corresponds to minimum
gain.
MIMO Applications
DESCRIPTION
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