PI6C2510-133LEX Pericom Semiconductor, PI6C2510-133LEX Datasheet

PI6C2510-133LEX

Manufacturer Part Number

PI6C2510-133LEX

Description

Phase Locked Loops (PLL) 1:9 Zero Delay Clock Driver

Manufacturer

Pericom Semiconductor

Type

Zero Delay PLL Clock Driverr

Datasheet

1.PI6C2510-133LEX.pdf (4 pages)

Specifications of PI6C2510-133LEX

Number Of Circuits

Maximum Input Frequency

150 MHz

Minimum Input Frequency

25 MHz

Supply Voltage (max)

3.6 V

Supply Voltage (min)

3 V

Maximum Operating Temperature

+ 70 C

Minimum Operating Temperature

0 C

Mounting Style

SMD/SMT

Operating Supply Voltage

3.3 V

Package / Case

TSSOP-24

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Current page: 1 of 4
Download datasheet (339Kb)

Features

• Operating Frequency up to 150 MHz

• Low-Noise Phase-Locked Loop Clock Distribution that meets

• Allows Clock Input to have Spread Spectrum modulation for

• Low jitter: Cycle-to-Cycle jitter ±75ps max.

• On-chip series damping resistor at clock output drivers for

• Operates at 3.3V VCC, 0–85°C

• Packages (Pb-free & Green available):

Block Diagram

Functional Table

– Plastic 24-pin TSSOP (L)

CLK_IN

133 MHz Registered DIMM Synchronous DRAM modules

for server/workstation/PC applications

EMI reduction

low noise and EMI reduction

FB_IN

AVcc

Inputs

09-0006

PLL

CLK_IN

Y[0:9]

Outputs

FB_OUT

CLK_IN

Y[0:9]

FB_OUT

Description

The PI6C2510-133E

phase-locked loop (PLL) clock driver, distributing high-frequency

clock signals for SDRAM and server applications. By connecting

the feedback FB_OUT output to the feedback FB_IN input, the

propagation delay from the CLK_IN input to any clock output

will be nearly zero. This zero-delay feature allows the CLK_IN

input clock to be distributed, providing one clock input to one

bank of ten outputs, with an output enable.

This clock driver is designed to meet the PC133 SDRAM

Registered DIMM speciﬁ cation. For test purposes, the PLL can

be bypassed by strapping AVCC to ground.

Pin Conﬁ guration

FB_OUT

Clock Driver with 10 Clock Outputs

AGND

GND

Low-Noise, Phase-Locked Loop

is a “enhanced,” low-skew, low-jitter,

24-Pin

PI6C2510-133E

PS8505B

CLK_IN

GND

FB_IN

11/18/09

Related parts for PI6C2510-133LEX

Related keywords

PI6C2510-133LEX datasheet
PI6C2510-133LEX data sheet
PI6C2510-133LEX pdf datasheet
PI6C2510-133LEX component
PI6C2510-133LEX part
PI6C2510-133LEX distributor
PI6C2510-133LEX RoHS
PI6C2510-133LEX datasheet download