PI6C2510-133E Pericom Semiconductor Corporation, PI6C2510-133E Datasheet

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PI6C2510-133E

Manufacturer Part Number
PI6C2510-133E
Description
3.3v, 150 Mhz, 10 Output Zero-delay Clock Driver For Sdram Dimm
Manufacturer
Pericom Semiconductor Corporation
Datasheet

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Features
• Operating Frequency up to 150 MHz
• Low-Noise Phase-Locked Loop Clock Distribution that
meets 133 MHz Registered DIMM Synchronous DRAM mod-
• Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
• Low jitter: Cycle-to-Cycle jitter ±75ps max.
• On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
• Operates at 3.3V VCC, 0–85°C
• Packages (Pb-free & Green available):
Block Diagram
Functional Table
CLK_IN
ules for server/workstation/PC applications
– Plastic 24-pin TSSOP (L)
FB_IN
AVcc
Inputs
07-0199
G
G
H
L
PLL
CLK_IN
Y[0:9]
L
Outputs
10
FB_OUT
CLK_IN
CLK_IN
Y[0:9]
FB_OUT
1
Description
The PI6C2510-133E is a “enhanced,” low-skew, low-jitter,
phase-locked loop (PLL) clock driver, distributing high-
frequency clock signals for SDRAM and server applications. By
connecting the feedback FB_OUT output to the feedback FB_IN
input, the propagation delay from the CLK_IN input to any
clock output will be nearly zero. This zero-delay feature allows
the CLK_IN input clock to be distributed, providing one clock
input to one bank of ten outputs, with an output enable.
This clock driver is designed to meet the PC133 SDRAM
Registered DIMM specifi cation. For test purposes, the PLL can
be bypassed by strapping AVCC to ground.
Pin Confi guration
Clock Driver with 10 Clock Outputs
FB_OUT
Low-Noise, Phase-Locked Loop
AGND
GND
GND
V
V
CC
CC
Y0
Y1
Y2
Y3
Y4
G
1
2
3
4
5
6
7
8
9
10
11
12
24-Pin
L
24
23
22
21
20
19
18
17
16
15
14
13
PI6C2510-133E
CLK_IN
AV
V
Y9
Y8
GND
GND
Y7
Y6
Y5
V
FB_IN
CC
CC
CC
PS8505B
08/30/07

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PI6C2510-133E Summary of contents

Page 1

... H CLK_IN 07-0199 Description The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high- frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero ...

Page 2

... Power Supply Test Conditions or GND GND GND PI6C2510-133E Low–noise, Phase –Locked Loop Clock Driver with 10 Clock Outputs Description Min. Max 0.5 CC –0.5 +5.0 100 1.0 –65 160 VCC Min Typ Max 3 ...

Page 3

... V Low level input voltage IL V Input Voltage I T Operating free-air temperature A Electrical Characteristics (Over recommended operating free-air temperature range.) Pull Up/Down Currents of PI6C2510-133E, VCC = 3.0V Symbol Pull-up current I CH Pull-up current Pull-down current I CIL Pull-down current AC Specifi cations - Timing requirements over recommended ranges of supply voltage and operating free-air temperature ...

Page 4

... Low–noise, Phase –Locked Loop Clock Driver with 10 Clock Outputs Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 • www.pericom.com Packaging Description 24-pin plastic TSSOP Pb-Free & Green 24-pin plastic TSSOP 25MHz - 150MHz 4 PI6C2510-133E Frequency Range 25MHz - 150MHz PS8505B 08/30/07 ...

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