PI6C2510-133 Pericom Semiconductor Corporation, PI6C2510-133 Datasheet
PI6C2510-133
Manufacturer Part Number
PI6C2510-133
Description
3.3v, 150 Mhz, 10 Output Zero-delay Clock Driver For Sdram Dimm
Manufacturer
Pericom Semiconductor Corporation
Datasheet
1.PI6C2510-133.pdf
(5 pages)
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1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Features
Block Diagram
Functional Table
CLK_IN
Operating Frequency up to 150 MHz
Low-Noise Phase-Locked Loop Clock Distribution that
meets 133 MHz Registered DIMM Synchronous DRAM
modules for server/workstation/PC applications
Allows Clock Input to have Spread Spectrum modulation
for EMI reduction
Zero Input-to-Output delay: Distribute one Clock Input
to one Bank of Ten outputs, with an output enable.
Low jitter: Cycle-to-Cycle jitter ±75ps max.
On-chip series damping resistor at clock output drivers
for low noise and EMI reduction
Operates at 3.3V V
Packaging(Pb-free & Green available):
- 24-pin TSSOP (L)
FB_IN
n I
AVcc
p
H
G
L
u
s t
G
C
[ Y
L
K
: 0
L
_
] 9
N I
CC
O
u
PLL
p t
u
F
s t
C
C
B
L
L
_
K
K
O
_
_
U
N I
N I
T
10
Y[0:9]
FB_OUT
1
Description
The PI6C2510-133 is a “quiet,” low-skew, low-jitter, phase-locked
loop (PLL) clock driver, distributing high-frequency clock signals
for SDRAM and server applications. By connecting the feedback
FB_OUT output to the feedback FB_IN input, the propagation
delay from the CLK_IN input to any clock output will be nearly zero.
This zero-delay feature allows the CLK_IN input clock to be
distributed, providing one clock input to one bank of ten outputs,
with an output enable.
This clock driver is designed to meet the PC133 SDRAM Registered
DIMM specification. For test purposes, the PLL can be bypassed
by strapping AV
Pin Configuration
Clock Driver with 10 Clock Outputs
FB_OUT
AGND
GND
GND
CC
V
V
Low-Noise, Phase-Locked Loop
CC
Y0
Y1
Y2
Y3
Y4
CC
G
to ground.
1
2
3
4
5
6
7
8
9
10
11
12
24-Pin
L
24
23
22
21
20
19
18
17
16
15
14
13
PI6C2510-133
CLK_IN
AV
V
Y9
Y8
GND
GND
Y7
Y6
Y5
V
FB_IN
CC
CC
CC
PS8383B
09/14/04
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PI6C2510-133 Summary of contents
Page 1
... Description The PI6C2510-133 is a “quiet,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. ...
Page 2
... PI6C2510-133 PS8383B 09/14/04 ...
Page 3
... Electrical characteristics over recommended operating free-air temperature range Pull Up/Down Currents of PI6C2510-133 ...
Page 4
... V ± ° – – PI6C2510-133 PS8383B 09/14/04 ...
Page 5
... Max SEATING PLANE .002 0.05 .006 0.15 .007 .012 0.19 0.30 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS Package Code L 24-pin TSSOP L Pb-free & Green, 24-pin TSSOP 5 PI6C2510-133 Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs .004 0.09 .008 0.20 0.45 .018 0.75 .030 .252 BSC 6.4 Package Type PS8383B 09/14/04 ...