723624L12PF Integrated Device Technology (Idt), 723624L12PF Datasheet

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723624L12PF

Manufacturer Part Number
723624L12PF
Description
FIFO Mem Sync Dual Bi-Dir 256 x 36 x 2 128-Pin TQFP
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.IDT723624L15PF8.pdf (35 pages)

Specifications of 723624L12PF

Package
128TQFP
Configuration
Dual
Bus Directional
Bi-Directional
Density
18 Kb
Organization
256x36x2
Data Bus Width
36 Bit
Timing Type
Synchronous
Typical Operating Supply Voltage
5 V
Operating Temperature
0 to 70 °C
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
EFA/ORA
FS1/SEN
FFA/IRA
Memory storage capacity:
Clock frequencies up to 83 MHz (8 ns access time)
Two independent clocked FIFOs buffering data in opposite
directions
Select IDT Standard timing (using EFA, EFB, FFA, and FFB flags
functions) or First Word Fall Through Timing (using ORA, ORB,
IRA, and IRB flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
FS0/SD
MRS1
A
MBF2
PRS1
CLKA
W/RA
SPM
MBA
0
CSA
ENA
AFA
AEA
-A
IDT723624
IDT723634
IDT723644
35
Control
Port-A
FIFO1,
Mail1
Reset
Logic
Logic
– 256 x 36 x 2
– 512 x 36 x 2
– 1,024 x 36 x 2
36
36
CMOS SyncBiFIFO
256 x 36 x 2,
512 x 36 x 2,
1,024 x 36 x 2
10
FIFO1
FIFO2
Programmable Flag
Offset Registers
36
Pointer
Pointer
Read
Write
36
Status Flag
Status Flag
RAM ARRAY
1,024 x 36
RAM ARRAY
1,024 x 36
256 x 36
512 x 36
256 x 36
512 x 36
Register
Register
Mail 1
Mail 2
Logic
Logic
1
Pointer
Pointer
Timing
Read
Write
Mode
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
• • • • •
TM
Serial or parallel programming of partial flags
Port B bus sizing of 36-bits (long word), 18-bits (word) and
9-bits (byte)
Big- or Little-Endian format for word and byte bus sizes
Master Reset clears data and configures FIFO, Partial Reset
clears data but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or coinci-
dent (simultaneous reading and writing of data on a single clock
edge is permitted)
Auto power down minimizes power dissipation
Available in space saving 128-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (–40° ° ° ° ° C to +85° ° ° ° ° C) is available
36
36
WITH BUS-MATCHING
36
36
OCTOBER 2008
FIFO2,
Mail2
Reset
Logic
Control
Port-B
Logic
IDT723624
IDT723634
IDT723644
3270 drw01
MBF1
EFB/ORB
AEB
FWFT
B
FFB/IRB
AFB
MRS2
PRS2
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
DSC-3270/4
0
-B
35

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723624L12PF Summary of contents

Page 1

CMOS SyncBiFIFO 256 512 1,024 FEATURES: • • • • • Memory storage capacity: IDT723624 – 256 IDT723634 – 512 ...

Page 2

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 DESCRIPTION: The IDT723624/723634/723644 is a monolithic, high-speed, low- power, CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies up ...

Page 3

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox register width matches the selected Port ...

Page 4

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port A Data I/O 36-bit bidirectional data port for side A. AEA Port A ...

Page 5

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O FS1/SEN Flag Offset I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset ...

Page 6

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted) Symbol V Supply Voltage Range CC V (2) Input ...

Page 7

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously ...

Page 8

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE (Commercial ± 10 ...

Page 9

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE 30PF (Commercial ± ...

Page 10

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 SIGNAL DESCRIPTION MASTER RESET (MRS1, MRS2) After power up, a Master Reset operation must be performed by providing a LOW ...

Page 11

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 performing a formal read operation. Refer to Figure 3 (Master Reset) for a First Word Fall Through select timing diagram. ...

Page 12

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are active outputs when both CSA and W/RA ...

Page 13

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag ...

Page 14

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 time t or greater after the write. Otherwise, the subsequent clock cycle SKEW1 can be the first synchronization cycle ...

Page 15

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a Port A read is ...

Page 16

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 BYTE ORDER ON PORT SIZE BYTE ORDER ON PORT SIZE H ...

Page 17

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA CLKB t RSTS MRS1 BE/FWFT SPM FS1,FS0 FFA/IRA EFB/ORB t RSF AEB t RSF AFA t RSF MBF1 NOTES: ...

Page 18

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA 1 4 MRS1, MRS2 t FSS t FSH SPM t FSS t FSH 0,0 FS1,FS0 FFA/IRA ENA A0-A35 CLKB ...

Page 19

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKA FFA/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ...

Page 20

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB FFB/IRB HIGH CSB W/RB MBB ENB B0-B17 DATA SIZE TABLE FOR WORD WRITES TO FIFO2 (1) SIZE MODE BM ...

Page 21

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t CLKH CLKB EFB/ORB HIGH CSB W/RB MBB ENB t EN B0-B35 (Standard Mode B0-B35 ...

Page 22

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB EFB/ORB HIGH CSB W/RB MBB t ENS2 ENB t MDV t EN B0-B8 (Standard Mode) t MDV OR t ...

Page 23

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA CSA LOW WRA HIGH t ENS2 MBA t ENS2 ENA IRA HIGH t DS A0-A35 W1 t SKEW1 CLKB ...

Page 24

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA CSA LOW WRA HIGH t t ENS2 MBA t t ENS2 ENA FFA HIGH A0-A35 W1 ...

Page 25

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENH ENS2 ENB IRB HIGH ...

Page 26

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB CSB LOW W/RB LOW t ENS2 t ENH MBB t t ENS2 ENH ENB FFB HIGH ...

Page 27

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB ORB HIGH B0-B35 Previous ...

Page 28

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB EFB HIGH B0-B35 Previous ...

Page 29

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA ORA HIGH A0-A35 Previous ...

Page 30

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA EFA HIGH A0-A35 Previous ...

Page 31

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA t t ENS2 ENH ENA t SKEW2 CLKB AEB X1 Words in FIFO1 ENB NOTES: is the minimum time ...

Page 32

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB t ENS2 ENB AFB [D-(Y2+1)] Words in FIFO2 CLKA ENA NOTES: is the minimum time between a rising CLKB ...

Page 33

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB t ENS1 CSB t ENS1 W/RB t ENS2 MBB t ENS2 ENB B0-B35 CLKA MBF2 CSA W/RA MBA ENA ...

Page 34

IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP ...

Page 35

ORDERING INFORMATION X XX XXXXXX Device Type Power Speed NOTE: 1. Industrial temperature range is available by special order. DATASHEET DOCUMENT HISTORY 10/04/2000 pgs. 1 through 35, except pgs. 20, 24-26, 32 and 33. 03/22/2001 pgs. 6 and 7. 08/01/2001 ...

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