723624L12PF Integrated Device Technology (Idt), 723624L12PF Datasheet - Page 25

• Manufacturer Part Number: 723624L12PF
• Description: FIFO Mem Sync Dual Bi-Dir 256 x 36 x 2 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723624L12PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 256x36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. t
2. If Port B size is word or byte, t
B0-B35
A0-A35
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
W/RA
CLKB
W/RB
CLKA
MBB
ORA
MBA
CSA
ENA
CSB
ENB
If the time between the CLKB edge and the rising CLKA edge is less than t
cycle later than shown.
SKEW1
IRB
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
FIFO2 Empty
LOW
LOW
HIGH
LOW
LOW
LOW
Figure 17. ORA Flag Timing and First Data Word Fall through when FIFO2 is Empty (FWFT Mode)
t
t
ENS2
ENS2
t
DS
SKEW1
W1
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
Old Data in FIFO2 Output Register
t
SKEW1
t
t
t
DH
ENH
ENH
(1)
t
CLKH
1
t
CLK
t
SKEW1
CLKL
t
, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
CLKH
25
2
t
CLK
t
REF
3
t
A
t
CLKL
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
REF
t
ENH
W1
3270 drw19