723624L12PF Integrated Device Technology (Idt), 723624L12PF Datasheet - Page 31

• Manufacturer Part Number: 723624L12PF
• Description: FIFO Mem Sync Dual Bi-Dir 256 x 36 x 2 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723624L12PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 256x36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTES:
1. t
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723624, 512 for the IDT723634, 1,024 for the IDT723644.
4. If Port B size is word or byte, t
NOTES:
1. t
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
NOTES:
1. t
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. If Port B size is word or byte, t
IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKB
CLKA
CLKB
CLKA
CLKB
CLKA
ENB
ENA
AEB
ENB
ENA
AFA
ENB
AEA
ENA
and rising CLKB edge is less than t
SKEW2
and rising CLKB edge is less than t
and rising CLKA edge is less than t
SKEW2
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
X1 Words in FIFO1
[D-(Y1+1)] Words in FIFO1
X2 Words in FIFO2
t
ENS2
t
ENS2
t
ENS2
Figure 23. Timing for AEB
Figure 24. Timing for AEA
SKEW2
Figure 25. Timing for AFA
SKEW2
is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.
is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
SKEW2
SKEW2
SKEW2
, then AFA may transition HIGH one CLKA cycle later than shown.
, then AEB may transition HIGH one CLKB cycle later than shown.
, then AEA may transition HIGH one CLKA cycle later than shown.
t
t
SKEW2
ENH
t
ENH
t
t
t
SKEW2
ENH
PAF
(1)
(1)
AEB
AEB
AEB
AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
AEA
AEA
AEA
AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
AFA
AFA
AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
AFA
1
1
t
ENS2
31
t
SKEW2
t
(D-Y1) Words in FIFO1
2
ENH
2
t
PAE
(1)
t
PAE
1
(X2+1) Words in FIFO2
COMMERCIAL TEMPERATURE RANGE
(X1+1) Words in FIFO1
t
t
ENS2
ENS2
2
t
PAF
t
t
ENH
t
ENH
PAE
t
PAE
3270 drw26
3270 drw 27
3270 drw25