XC6SLX45T-3FGG484C Xilinx Inc, XC6SLX45T-3FGG484C Datasheet - Page 50

• Manufacturer Part Number: XC6SLX45T-3FGG484C
• Description: FPGA Spartan®-6 Family 43661 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXTr

Specifications of XC6SLX45T-3FGG484C

• Package: 484FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 43661
• Device Logic Units: 27288
• Number Of Registers: 54576
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 296
• Ram Bits: 2138112
• Package / Case: 484-BGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Number Of I /o: 296
• Number Of Logic Elements/cells: 43661
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DCM Switching Characteristics
Table 51: Operating Frequency Ranges and Conditions for the Delay-Locked Loop (DLL)
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
4.
5.
Input Frequency Ranges
CLKIN_FREQ_DLL
Input Pulse Requirements
CLKIN_PULSE
Input Clock Jitter Tolerance and Delay Path Variation
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL
CLKFB_DELAY_VAR_EXT
DLL specifications apply when using any of the DLL outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV.
When operating independently of the DLL, the DFS supports lower CLKIN_FREQ_DLL frequencies. See
The CLKIN_DIVIDE_BY_2 attribute increases the effective input frequency range. When set to TRUE, the input clock frequency is divided by two as
it enters the DCM. Input clock frequencies for the clock buffer being used can be increased up to the F
BUFIO2 limits). When used with CLK_FEEDBACK=2X, the input clock frequency matches the frequency for CLK2X, and is limited to
CLKOUT_FREQ_2X.
CLKIN_FREQ_DLL input jitter beyond these limits can cause the DCM to lose LOCK, indicated by the LOCKED output deasserting. The user must
then reset the DCM.
When using both DCMs in a CMT, both DCMs must be LOCKED.
Symbol
Frequency of the CLKIN clock
Cycle-to-cycle jitter at the CLKIN
input when the CLKDV output is
not used.
Frequency of the CLKIN clock
input when using the CLKDV
output.
CLKIN pulse width as a
percentage of the CLKIN period
for
CLKIN_FREQ_DLL < 150 MHz
CLKIN pulse width as a
percentage of the CLKIN period
for
CLKIN_FREQ_DLL > 150 MHz
input for
CLKIN_FREQ_DLL < 150 MHz
Period jitter at the CLKIN input.
Allowable variation of the off-chip
feedback delay from the DCM
output to the CLKFB input.
Cycle-to-cycle jitter at the CLKIN
input for
CLKIN_FREQ_DLL > 150 MHz.
Description
(4)
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Min
5
5
40
45
–
–
–
–
(2)
(2)
-3
280
280
±300
±150
Max
60
55
±1
±1
(3)
(3)
Min
5
5
40
45
–
–
–
–
(2)
(2)
-3N
Speed Grade
280
280
±300
±150
Max
60
55
±1
±1
(3)
(3)
MAX
Table
(see
Min
5
5
40
45
–
–
–
–
(2)
(2)
Table 47
53.
-2
(1)
250
250
±300
±150
Max
60
55
±1
±1
(3)
(3)
and
Min
Table 48
5
5
40
45
–
–
–
–
(2)
(2)
-1L
175
133
±300
±150
Max
for BUFG and
60
55
±1
±1
(3)
(3)
Units
MHz
MHz
ps
ps
ns
ns
%
%
50