XC6SLX45T-3FGG484C Xilinx Inc, XC6SLX45T-3FGG484C Datasheet - Page 61

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XC6SLX45T-3FGG484C

Manufacturer Part Number
XC6SLX45T-3FGG484C
Description
FPGA Spartan®-6 Family 43661 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer
Xilinx Inc
Series
Spartan® 6 LXTr
Datasheet

Specifications of XC6SLX45T-3FGG484C

Package
484FBGA
Family Name
Spartan®-6
Device Logic Cells
43661
Device Logic Units
27288
Number Of Registers
54576
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
296
Ram Bits
2138112
Package / Case
484-BGA
Mounting Type
Surface Mount
Voltage - Supply
1 V ~ 3.6 V
Operating Temperature
0°C ~ 85°C
Number Of I /o
296
Number Of Logic Elements/cells
43661
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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0
Table 67: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode
and PLL in DCM2PLL Mode.
T
ICKOFDCM0_PLL
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible
IOB and CLB flip-flops are clocked by the global clock net.
DCM and PLL output jitter are already included in the timing calculation.
Symbol
Global Clock and OUTFF with DCM and PLL
Description
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
XC6SLX4
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX25T
XC6SLX45
XC6SLX45T
XC6SLX75
XC6SLX75T
XC6SLX100
XC6SLX100T
XC6SLX150
XC6SLX150T
Device
5.58
5.58
5.50
5.57
5.57
5.53
5.53
5.55
5.55
5.58
5.62
5.32
5.32
-3
6.19
6.06
6.04
6.04
5.97
5.97
6.00
6.00
6.03
6.03
5.70
5.70
Speed Grade
N/A
-3N
7.42
7.42
7.05
7.02
7.02
6.96
6.96
6.99
6.99
7.02
7.02
6.41
6.41
-2
8.54
8.54
8.24
8.33
8.32
8.54
9.11
8.26
N/A
N/A
N/A
N/A
N/A
-1L
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
61

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